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Issue #1157

Auto-alignment on comments in PORT declaration

Added by CHOON LIN LEE almost 3 years ago. Updated over 2 years ago.

Status:
Feature
Priority:
Normal
Assignee:
-
Category:
Indents
% Done:

0%


Description

Original Code

module top ( //Inputs input CLK, //System Clock input RST, //Active High Reset input [3:0] CONTROL, //Control decoder.

//Outputs
output reg [7:0] LIVE_DATA, //1 byte data
output VALID  //Valid Flag
);

Is there any feature to auto-align the comments? After auto-align comments, it should be as below: module top ( //Inputs input CLK, //System Clock input RST, //Active High Reset input [3:0] CONTROL, //Control decoder.

//Outputs
output reg [7:0] LIVE_DATA,//1 byte data
output VALID               //Valid Flag 
);

Having issues to align those comments especially the source is from other text editor. EMACS Verilog mode will mis-align the comments for port declaration part.

Capture.PNG View - Code with auto-align comment (16.6 KB) CHOON LIN LEE, 04/14/2017 05:57 AM

History

#1 Updated by CHOON LIN LEE almost 3 years ago

After auto align the comments, it should be like below:

#2 Updated by Wilson Snyder over 2 years ago

  • Status changed from New to Feature
  • Assignee deleted (Michael McNamara)

I can see the usefulness. If you want to make a patch we'll consider it, otherwise note there is no present active development of new indentation features, so you're in for a long wait.

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