Author Name: CHOON LIN LEE
Original Redmine Issue: 1157 from https://www.veripool.org

Original Code

module top
(
//Inputs
input CLK, //System Clock
input RST, //Active High Reset
input [3:0] CONTROL, //Control decoder.

//Outputs
output reg [7:0] LIVE_DATA, //1 byte data
output VALID //Valid Flag
);

Is there any feature to auto-align the comments? After auto-align comments, it should be as below:
module top
(
//Inputs
input CLK, //System Clock
input RST, //Active High Reset
input [3:0] CONTROL, //Control decoder.

//Outputs
output reg [7:0] LIVE_DATA,//1 byte data
output VALID //Valid Flag
);

Having issues to align those comments especially the source is from other text editor. EMACS Verilog mode will mis-align the comments for port declaration part.