Id:   26999
Status:		rejected
Queue: 		Verilog-Perl
Severity:	Normal
Broken in: 	2.373
Requestors:	NODINE <nodine@>
X Attachments
no_newline.v

     * Tue May 08 11:28:00 2007 (14b) by NODINE

Created:	Tue May 08 11:27:58 2007
Last Contact: 	Tue May 08 11:41:03 2007
Closed: 	Wed May 16 09:52:01 2007
Updated: 	Wed May 16 09:52:03 2007 by WSNYDER

Subject:  Verilog::Preproc requires newline at end of file
Verilog::Preproc returns an error
%Error: ../testsuite/no_newline.v:1: EOF (missing return?) in define value
because there is no newline at the end of file. One of the source
verilog files in a common commercially licensed core has this issue.
There should be some option that allows suppressing this error.
Subject:     no_newline.v
Download no_newline.v [application/tkgate 14b]
Message body not shown because it is too large or is not plain text.

The IEEE spec states in 19.3.1 that

"The first newline not preceeded by a backslash shall end the macro text."

Since their define never has a newline, their code is wrong.

I don't want to add options to parse code that violates the spec and is
also exceedingly uncommon (since I've only seen it once ever.)

Sorry.

Subject:    Re: [rt.cpan.org #26999] Verilog::Preproc requires newline at end of file
Date: 	    Tue, 08 May 2007 10:40:40 -0500
To: 	    bug-Verilog-Perl@
From: 	    Mark Nodine <nodine@>
That's reasonable. I guess we should report the error to the
company that produced the Verilog.

Thanks.