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Issue #1163

Module mis-indent within generate statement

Added by Brad Dobbie over 2 years ago. Updated over 2 years ago.

Status:
Confirmed
Priority:
Normal
Assignee:
-
Category:
Indents
% Done:

0%


Description

I've encountered an indentation problem, shown below. verilog-mode-version is "2017-04-28-6b4fc78-vpo". I'm pretty sure this problem wasn't present in previous versions, but I can't say for sure.

Notice the opening parenthesis of the instance port connections is indented way too far. If I remove the "=0" on the generate for (...), the indentation works correctly (but obviously that isn't valid syntax).

module indent;

   // Here, AUTOINST line indents incorrectly indents way too far the the right
   generate for (genvar i=0; i<4; i++) begin : gen_inst0
      subindent s
                          (/*AUTOINST*/
                           // Outputs
                           .y                           (y),
                           // Inputs
                           .a                           (a));
   end endgenerate

   // Without the '=0', the AUTOINST line indents properly
   generate for (genvar i; i<4; i++) begin : gen_inst1
      subindent s
        (/*AUTOINST*/
         // Outputs
         .y                             (y),
         // Inputs
         .a                             (a));
   end endgenerate

endmodule

module subindent (input a, output y);
endmodule

indent.v (582 Bytes) Brad Dobbie, 05/16/2017 02:21 PM

History

#1 Updated by Wilson Snyder over 2 years ago

  • Category set to Indents
  • Status changed from New to Confirmed

FYI I looked at old revisions and didn't find any that work with the last 2 years.

#2 Updated by Kaushal Modi over 2 years ago

I confirm this issue too.

I never saw this issue earlier though as my coding style is a bit different.

Below indents fine.
module indent;

   genvar i;
   generate
      for (i=0; i<4; i++) begin : gen_inst0
         subindent s
             (/*AUTOINST*/
              // Outputs
              .y                           (y),
              // Inputs
              .a                           (a));
      end 
   endgenerate

endmodule

module subindent (input a, output y);
endmodule

#3 Updated by Wilson Snyder over 2 years ago

Test committed as indent_genmod.v. Kaushal, perhaps you could take a look when you get a chance?

#4 Updated by Brad Dobbie over 2 years ago

Kaushal Modi wrote:

I confirm this issue too.

I never saw this issue earlier though as my coding style is a bit different.

Below indents fine. [...]

Kashul, the issue is still present in your coding style but it is harder to see. If I space out the for statement, you can see the open parenthesis getting aligned with the = sign.

   genvar i;
   generate
      for                          (i=0; i<4; i++) begin : gen_inst0
         subindent s
                                      (/*AUTOINST*/
                                       // Outputs
                                       .y                           (y),
                                       // Inputs
                                       .a                           (a));
      end 
   endgenerate

#5 Updated by Kaushal Modi over 2 years ago

@Wilson: I cannot promise when, but I am putting this on my list to investigate. My long term goal is to document all the regexp defvars. That exercise should help fix issues like these :)

@Brad: You're right. I'll have a look at this when I get chance. Debugging indentation logic is a bit involved.

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