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Module mis-indent within generate statement #1163
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Original Redmine Comment FYI I looked at old revisions and didn't find any that work with the last 2 years. |
Original Redmine Comment I confirm this issue too. I never saw this issue earlier though as my coding style is a bit different. Below indents fine.
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Original Redmine Comment Test committed as indent_genmod.v. Kaushal, perhaps you could take a look when you get a chance? |
Original Redmine Comment Kaushal Modi wrote:
Kashul, the issue is still present in your coding style but it is harder to see. If I space out the for statement, you can see the open parenthesis getting aligned with the = sign.
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Original Redmine Comment @wilson: I cannot promise when, but I am putting this on my list to investigate. My long term goal is to document all the regexp defvars. That exercise should help fix issues like these :) @brad: You're right. I'll have a look at this when I get chance. Debugging indentation logic is a bit involved. |
I took a look at this because it was bugging me.
the term of interest appears to be "\([A-Za-z_][A-Za-z0-9_]\s-=\s-*\)?" it matches the genvar assignment in the for loop "i=0". the indention after that point is aligned with the value so where ever the '=' sign is the key. here is the stack trace:
I don't know the purpose of that term in the regexp. so not sure what the next steps should be. Update, I removed that expression and it did not change the indent level.
it caught the "for" term and then searched forward for an '='. I tried putting something, i used an always_comb, before the instance and that fixed the indenting of the instance port list. Is there a way to check for an "instance" in the search for beginning of statement? |
This code works for the scenarios I tried. I have never contributed before not sure the process:
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Thanks for looking at improving the indents. Unfortunately there's no longer anyone super familiar with the indent code to provide insights as to the past. This code seems to be looking to the =, which doesn't seem right, I would think that if the "mod" is properly being indented the next line should follow with appropriate relative indent. As to contributing, it's best to make a pull request, search for "github pull request tutorial" or similar - they'll describe the process better than I would ;) |
Indentation within implicit generate/endgenerate blocks is definitely wonky. Can you confirm that explicit generate/endgenerate indents correctly?
… generate genvar i;
for(i=...)
...
endgenerate
Sent from my iPhone
On Oct 18, 2020, at 10:17, Wilson Snyder ***@***.***> wrote:
Thanks for looking at improving the indents.
Unfortunately there's no longer anyone super familiar with the indent code to provide insights as to the past.
This code seems to be looking to the =, which doesn't seem right, I would think that if the "mod" is properly being indented the next line should follow with appropriate relative indent.
As to contributing, it's best to make a pull request, search for "github pull request tutorial" or similar - they'll describe the process better than I would ;)
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I created a pull request. |
Looking backwards like this seems overly sensitive note one of the regression tests is now failing. The traditional approach is to look forward adjusting the indent appropriately, but as noted I haven't been in this code much perhaps @acr4 can comment. |
I think it does the backward search since it is classified as a continuing expression. it is search backward to determine the exact nature of the expression. |
Author Name: Brad Dobbie
Original Redmine Issue: 1163 from https://www.veripool.org
I've encountered an indentation problem, shown below. verilog-mode-version is "2017-04-28-6b4fc78-vpo". I'm pretty sure this problem wasn't present in previous versions, but I can't say for sure.
Notice the opening parenthesis of the instance port connections is indented way too far. If I remove the "=0" on the generate for (...), the indentation works correctly (but obviously that isn't valid syntax).
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