Author Name: Cliff Kaku
Original Redmine Message: 2224 from https://www.veripool.org

if I defined a signal pattern twice, does the second one overwrite the first one?
Example
/* module_A AUTO_TEMPLATE (
.pin1_sub (wire_A),
.(.*)_sub (wire_B),
);
*/
module_A inst_module_A (/AUTOINST/);

So, which wire will be connected to pin1_sub?

Thanks!