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Issue #1167

Port list is not aligned properly when the first port declaration is not start from a new line

Added by Enzo Chi over 2 years ago. Updated about 2 years ago.

Status:
Confirmed
Priority:
Normal
Assignee:
-
Category:
Indents
% Done:

0%


Description

Found a issue of align the port list: (verilog-auto-lineup 'all)

When the first port declaration right after "(" as example below, the port name is not aligned correctly.

Port "sel" and the rest are not aligned.
module indent_case(input bit [1:0] sel,
                   input byte  a,
                   input byte  b,
                   input byte  c,
                   input byte  d,
                   output byte dout
                   );
Expect to be
module indent_case(input bit [1:0] sel,
                   input byte      a,
                   input byte      b,
                   input byte      c,
                   input byte      d,
                   output byte     dout
                   );

If "sel" declaration start from a new line, it works

module indent_case(
                   input bit [1:0] sel,
                   input byte      a,
                   input byte      b,
                   input byte      c,
                   input byte      d,
                   output byte     dout
                   );

indent_case.sv (1.43 KB) Enzo Chi, 05/26/2017 03:52 AM

History

#1 Updated by Wilson Snyder about 2 years ago

  • Category set to Indents
  • Status changed from New to Confirmed

AFAIK still a problem, perhaps someone would like to contribute a patch?

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