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Port list is not aligned properly when the first port declaration is not start from a new line #1167

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veripoolbot opened this issue May 26, 2017 · 1 comment · Fixed by #1771
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Port list is not aligned properly when the first port declaration is not start from a new line #1167

veripoolbot opened this issue May 26, 2017 · 1 comment · Fixed by #1771
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@veripoolbot
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Author Name: Enzo Chi
Original Redmine Issue: 1167 from https://www.veripool.org

Found a issue of align the port list: (verilog-auto-lineup 'all)

When the first port declaration right after "(" as example below, the port name is not aligned correctly.

Port "sel" and the rest are not aligned.

module indent_case(input bit [1:0] sel,
                    input byte  a,
                    input byte  b,
                    input byte  c,
                    input byte  d,
                    output byte dout
                    );

Expect to be

module indent_case(input bit [1:0] sel,
                    input byte      a,
                    input byte      b,
                    input byte      c,
                    input byte      d,
                    output byte     dout
                    );

If "sel" declaration start from a new line, it works

module indent_case(
                    input bit [1:0] sel,
                    input byte      a,
                    input byte      b,
                    input byte      c,
                    input byte      d,
                    output byte     dout
                    );
@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-11-19T13:38:15Z

AFAIK still a problem, perhaps someone would like to contribute a patch?

@gmlarumbe gmlarumbe mentioned this issue Jun 9, 2022
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gmlarumbe added a commit that referenced this issue Jun 13, 2022
@gmlarumbe
Fix alignment of first port declaration (#1167) (#1771).
27a23af 
* verilog-mode.el (verilog-get-lineup-indent, verilog-pretty-declarations):
Fix alignment of first port declaration (#1167) (#1771).

Signed-off-by: Gonzalo Larumbe <gonzalomlarumbe@gmail.com>
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Fix alignment of first port declaration gmlarumbe/verilog-mode
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