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Author Name: Wilder Ness Original Redmine Message: 2245 from https://www.veripool.org
I have code where interfaces are declared in the port declaration part. How do I get rid of the reg declaration below?
module a ( input x, input y, output z, my_interface.some local_if )
/*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg my_interface; // End of automatics assign local_if.port_a = 1'b0;
endmodule
The text was updated successfully, but these errors were encountered:
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Author Name: Wilder Ness
Original Redmine Message: 2245 from https://www.veripool.org
I have code where interfaces are declared in the port declaration part. How do I get rid of the reg declaration below?
module a (
input x,
input y,
output z,
my_interface.some local_if
)
endmodule
The text was updated successfully, but these errors were encountered: