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Implicit port connection .* does not work for interfaces #1176

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veripoolbot opened this issue Jun 20, 2017 · 4 comments
Closed

Implicit port connection .* does not work for interfaces #1176

veripoolbot opened this issue Jun 20, 2017 · 4 comments
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resolution: fixed Closed; fixed

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Author Name: Maciej Piechotka
Original Redmine Issue: 1176 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

The following code does not compile with error @can't find definition of signal, again: if@. It does work with manual unrolling to @my_module mod(.if(if), .*);@.

module foo;
    my_if if;
    my_module mod(.*);
endmodule
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-06-20T01:34:21Z

"if" is a Verilog keyword. Perhaps you oversimplified the example, if so please attach a complete example (not using "if") that fails.

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Original Redmine Comment
Author Name: Maciej Piechotka
Original Date: 2017-06-20T03:34:09Z

Wilson Snyder wrote:

"if" is a Verilog keyword. Perhaps you oversimplified the example, if so please attach a complete example (not using "if") that fails.

module videotest_config_test(
	input  logic    aclk,
     input  logic    arst,
     input  cnt_t    cnt,
     output vsize_t  vsize,
     output hsize_t  hsize,
     input  logic    idle,
     output logic    intr
	);
     axi_lite conf(aclk, arst);
     ack_sign stop();

	videotest_config dut(/*.conf(conf), .stop(stop),*/ .*); // Doesn't work in Verilator without comment
endmodule

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-06-20T22:40:47Z

Fixed in git towards 3.905.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-06-22T22:38:10Z

In 3.906.

@veripoolbot veripoolbot added the resolution: fixed Closed; fixed label Dec 22, 2019
@wsnyder wsnyder mentioned this issue May 3, 2020
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