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Verilog::SigParser problems with package ordering #1179
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Original Redmine Comment The language standard requires packages be declared before they are referenced, so most likely that's resulting in this message. Include the packages before you use them. |
Original Redmine Comment So what's the best way to use SigParser? How do you build the file tree such that it parses in the correct order? I just assumed it would work like Verilog::Netlist if you passed in a VC file. |
Original Redmine Comment It does work like Netlist. You just need the file list in the proper order, with files containing packages first, or have your modules `include the package definitions, just as most simulators require. |
Original Redmine Comment Our VC file has all the packages declared at the head of the file. So what you're saying is that if you want to use SigParser, you have to manually build the file tree or update the source to `include? Edit: I tried to `include the package but then I get an 'unexpect package' error from SigParse. |
Original Redmine Comment Fixed it. I remembered that when parsing the options file using Verilog::Getopt->parameter, it returns a list of files. This is how we get the packages in our other scripts. Thanks. |
Original Redmine Comment Great! |
Author Name: Shareef Jalloq
Original Redmine Issue: 1179 from https://www.veripool.org
Hi there,
I'm seeing an error reported when trying to parse a file that uses wildcard imports. It seems strange as vppreproc and Verilog::Netlist both parse these fine. I'm using version 3.422.
The error is:
The script looks like:
The text was updated successfully, but these errors were encountered: