Author Name: Arthur Kahlich
Original Redmine Issue: 1180 from https://www.veripool.org

Original Assignee: Arthur Kahlich

Why I need this: I have a design that uses a Verilog ROM construct to specify a decoder from opcode to control signals, where for some of the opcode values a control signal output value may be a don't care, and in fact should be don't care for logic minimization at synthesis. It is more convenient to generate Verilog ROM initialization files than it is to generate what may be many, massive and verbose Verilog case statements to initialize these ROMs.

The IEEE Std. 1364.1-2002, section 5.5 states that 'x' values are supported when on expression RHS as don't care indicators.

I made a small addition to verilated.cpp to enable this capability for myself. The patch file is attached.