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Plusargs verilog compilation #1181
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Original Redmine Comment VL_VALUEPLUSARGS_IW should no longer be used; it's somewhat surprising the compiler is complaining, but I removed the old functions from verilated.cpp, please try the git head. |
Original Redmine Comment Hi Wilson Thanks for a prompt update. I rebuilt Verilator from master after your latest commit. Now got another error: ../main.cpp: In function ‘int main(int, char**, char**)’: ../main.cpp:40:6: note: suggested alternative: ‘VL_VALUEPLUSARGS_INI’ Compiler is GCC 7.1 under Ubuntu 14.04.5 |
Original Redmine Comment NOTE: This is NOT a compile error. I built Verilator seamlessly. I get this error when I compile my RTL and trying to run the simulation |
Original Redmine Comment I suspect you are verilating with one version of verilator, then compiling that output pointing at a different version's includes. |
Original Redmine Comment Hi Wilson Wrong assumption. Do you want me to upload my Verilator build ? |
Original Redmine Comment I've been using Verilator for ages with the same Makefile and have no issues with verilator_3_902 |
Original Redmine Comment There is no longer any occurrence of VL_VALUEPLUSARGS_IQ in the verilator sources, and the internal tests that use plusargs work. Therefore I am presuming there's something wrong in your setup, perhaps picking up an older version. However perhaps I'm missing something, and if you can modify the test_regress/t/t_sys_plusargs.v to show the problem, I'll fix it. |
Original Redmine Comment Wilson, pls take a careful look at the error. It complains on VL_VALUEPLUSARGS_II, not VL_VALUEPLUSARGS_IQ. |
Original Redmine Comment Your message said "main.o: In function `VL_VALUEPLUSARGS_IQ". Regardless, please modify the test_regress/t/t_sys_plusargs.v to show the problem, and I'll fix it. |
Original Redmine Comment The first error from the ticket description has gone. I'm now talking about another issue, reported in #2. Okay, will update the plusargs test and be right back soon. Thanks for support |
Original Redmine Comment I just built verilator_3_906-8-g13f7903. I ran standard tests and they all have passed. GCC 7.1 complains on line 40 in the main.cpp attached. The issue is in the random seed initialization with the VL_VALUEPLUSARGS_II method. |
Original Redmine Comment Oh, so it's your code that's calling it, not verilator. That makes a lot more sense then. VL_ functions occasionally change, and while changes are avoided they do sometimes need to change, so if you're using them you'll need to keep up to date. Use instead VL_VALUEPLUSARGS_INI(32, "randseed=%d", randomSeed); |
Original Redmine Comment Thank you! That resolves my problem |
Original Redmine Comment In 3.908. |
Author Name: Thomas J Whatson
Original Redmine Issue: 1181 from https://www.veripool.org
Dear Community
I've got a compilation error with the following message:
main.o: In function
VL_VALUEPLUSARGS_IQ(int, char const*, char, unsigned long&)': main.cpp:(.text._Z19VL_VALUEPLUSARGS_IQiPKccRm[VL_VALUEPLUSARGS_IQ(int, char const*, char, unsigned long&)]+0x2a): undefined reference to
VL_VALUEPLUSARGS_IW(int, char const*, char, unsigned int*)'collect2: error: ld returned 1 exit status
I use Verilog $value$plusargs task to pass extra parameters during simulation.
I use the latest Verilog Perl and SystemPerl. Veriloator is verilator_3_906-7-g70daadf.
The system is Ubuntu 14.04 64 bit with GCC 7.1
I had NO this issue in 3.902 version. Pls fix this
Thank you
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