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Issue #1184

Verilator doesn't detect multiple assignment

Added by Dan Gisselquist over 1 year ago. Updated over 1 year ago.

Status:
Feature
Priority:
Normal
Assignee:
-
Category:
Lint
% Done:

0%


Description

Consider the following code, first <A HREF="https://www.veripool.org/boards/3/topics/2282-Verilator-Verilator-doesn-t-detect-multiple-assignment">posted on the forum</A>:

module tst(i_clk, i_val, o_a, o_b);
        input   wire    i_clk;
        input   wire    i_val;
        output  reg     o_a, o_b;

        always @(posedge i_clk)
                if ((i_val)&&(!o_a))
                        o_b <= 1'b0;

        always @(posedge i_clk)
                if ((i_val)&&(o_a))
                        o_b <= 1'b1;

        always @(posedge i_clk)
                o_a <= i_val;

endmodule

Notice how o_b is being set to contradictory values. I'd like to recommend that Verilator check for this.

I've searched through V3Delayed.cpp, seen the MULTIDRIVEN logic, thought to try to fix it but ... I'm still struggling to figure out what's going on. ;) I know, it can't be too hard ... I know what an AST is, I know what a parser is, etc., I just ... haven't figured it out yet. Oh, ok, here it is ... just found the defn of an ActiveAST ... I think I see the problem now, I just don't (yet) know how I might fix it.

Dan

Dan

History

#1 Updated by Wilson Snyder over 1 year ago

  • Status changed from New to Feature

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