Original Redmine Comment
Author Name: Rob Stoddard
Original Date: 2017-08-03T16:38:54Z

Here is a sample design that shows the error I mentioned... The full build output I'm getting here is:

verilator -Wno-UNOPTFLAT -Wno-DECLFILENAME -Wno-ASSIGNDLY -Wno-fatal +1800-2012ext+sv --relative-includes -CFLAGS -g -CFLAGS -std=c++11 --cc design/Orchestrate/top.sv --exe --top-module top -LDFLAGS -static-libgcc -LDFLAGS -static-libstdc++ -LDFLAGS -ltcl -LDFLAGS -lpthread
%Warning-PINMISSING: design/Orchestrate/top.sv:25: Cell has missing pin: p_ss00p00h_vdd
%Warning-PINMISSING: Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.
%Warning-PINMISSING: design/Orchestrate/top.sv:25: Cell has missing pin: p_ss00p00h_gnd
%Error: Internal Error: design/Orchestrate/top.sv:25: ../V3Slice.cpp:407: Couldn't find a VarRef on the LHSP of an Assign
%Error: Command Failed /usr/local/bin/verilator_bin -Wno-UNOPTFLAT -Wno-DECLFILENAME -Wno-ASSIGNDLY -Wno-fatal +1800-2012ext+sv --relative-includes -CFLAGS -g -CFLAGS '-std=c++11' --cc design/Orchestrate/top.sv --exe --top-module top -LDFLAGS -static-libgcc -LDFLAGS -static-libstdc++ -LDFLAGS -ltcl -LDFLAGS -lpthread
make: *** [Makefile:31: verilator] Error 10

Of course, this is a do-nothing design (now that I've hacked out all the company sensitive material) ... but the error remains quite apparent. Now, I do have various width, pinmissing, and even a few multdriven (although the logic oddly enough doesn't drive from multiple sources... I have checked it! ... and the design works fine in Verilator sim...) warnings on the original design, and I'd like to get the designers to defray a lot of those warnings... so I wonder if there's a warning situation that can eventually cause a problem with /verilator public/ ...

Thank you
Rob Stoddard

Original Redmine Comment
Author Name: Rob Stoddard
Original Date: 2017-08-04T04:52:57Z

It turns out that the issue has something to do with inout ports in the module within which /verilator public/ is called. I will get a few simple examples in the AM.

Original Redmine Comment
Author Name: Rob Stoddard
Original Date: 2017-08-04T16:54:04Z

It turns out that if an inout is unassigned then there are problems. I had two signals in the original design that were unassigned (vdd and gnd) and were causing this issue to happen. Note that the pins that are marked /verilator public/ do not have to have any connection at all with the inout lines that are unassigned, as long as the signal that's marked /verilator public/ is in a module with the unassigned inout or in a module instantiated within the module with the unassigned inout.

I tried creating the same issue with an output that's unassigned and the issue did not happen.

So in my company's design, we commented out the vdd and gnd signals coming inout of top and are moving on with life. Wilson Snyder, you've got my email address if there's any need for more information.

`timescale 1ns/100ps

module sub_mod (
         data   , // Data Input
         clk    , // Clock Input
         reset  , // Reset input
         q,        // Q output
         test_inout,
         test_out
);
  //-----------Input Ports---------------


input [7:0] data /*verilator public*/;

input clk, reset ;

inout test_inout;  // Get rid of this, the problem goes away.

  //-----------Output Ports---------------
output [7:0] q;

output test_out;  // Not assigned,  no problem.

logic [7:0] que;


// Uncomment this line, the error goes away.
//assign test_inout = que;

assign q = que;
always @ ( posedge clk)
if (~reset) begin
         que <= 8'b0;
end  else begin
         que <= data;
end

endmodule


module top    (
         out      ,  // Output of the counter
         up_down  ,  // up_down control for counter
         clk      ,  // clock input
         data     ,  // Data to load
         reset       // reset input
);
  //----------Output Ports--------------
output [7:0] out;
  //------------Input Ports--------------
  //input [7:0] data ;
input [7:0] data;
input up_down, clk, reset;
  //------------Internal Variables--------
reg [7:0] out;
logic q_out;
  //-------------Code Starts Here-------
always @(posedge clk)
if (reset) begin // active high reset
         out <= 8'b0 ;
end else if (up_down) begin
         out <= out + 1;
end else begin
         out <= q_out;
end

sub_mod sub_mod
(
         .clk(clk),
         .data(data),
         .reset(reset),
         .q(q_out)
);

endmodule

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-08-13T22:09:46Z

Fixed in git towards 3.907.

I added an "lvalue" assertion that flags the (previous) problem earlier, hopefully it won't have any false positives, if so please file another bug.

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-08-29T02:54:11Z

In 3.908.