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indent error in the block of autoreset while parameterized the width of register #1188
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Original Redmine Comment hi, Before I go further, I want to say that Verilog mode has changed my life. I've taken a look at the Verilog-Mode FAQ at And, I've considered filing the bug on the issue tracker at So, to reproduce the bug, start a fresh Emacs via emacs
Given those lines, I expected [[whole buffer been indented by c-x h tab]] to happen; == The code: ==
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Original Redmine Comment Sorry forgot to thank you for the bug report and close this out, this was fixed with #�. |
Original Redmine Comment Wilson Snyder wrote:
#� can't fix my situation, and I try to fix this by folloing in the funciton verilog-at-constraint-p,
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Original Redmine Comment Thanks for the patch, applied to git and verilog-mode-2018-08-21-08b745f-vpo |
Author Name: yun he
Original Redmine Issue: 1188 from https://www.veripool.org
hello
I want to report a bug.
Before I go further, I want to say that Verilog mode has changed my life.
I save so much time, my files are colored nicely, my co workers respect
my coding ability... until now. I'd really appreciate anything you
could do to help me out with this minor deficiency in the product.
I've taken a look at the Verilog-Mode FAQ at
http://www.veripool.org/verilog-mode-faq.html.
And, I've considered filing the bug on the issue tracker at
http://www.veripool.org/verilog-mode-bugs
since I realize that public bugs are easier for you to track,
and for others to search, but would prefer to email.
So, to reproduce the bug, start a fresh Emacs via emacs
-no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
the code included below.
module test (/AUTOARG/
// Inputs
i_blc, I_cdef
) ;
input i_blc, I_cdef;
reg [par_a -1:0] b,c;
endmodule // test
Given those lines, I expected [[whole buffer be indented by c-x h tab]] to happen;
but instead, [[below]] happens!.
== The code: ==
module test (/AUTOARG/
// Inputs
i_blc, I_cdef
) ;
input i_blc, I_cdef;
reg [par_a -1:0] b,c;
endmodule // test
Emacs : GNU Emacs 24.5.1 (i686-pc-mingw32)
of 2015-04-11 on LEG570
Package: verilog-mode v2017-07-14-c36a886-vpo
current state:
(setq
verilog-active-low-regexp nil
verilog-after-save-font-hook nil
verilog-align-ifelse nil
verilog-assignment-delay ""
verilog-auto-arg-sort nil
verilog-auto-declare-nettype nil
verilog-auto-delete-trailing-whitespace nil
verilog-auto-endcomments t
verilog-auto-hook nil
verilog-auto-ignore-concat nil
verilog-auto-indent-on-newline t
verilog-auto-inout-ignore-regexp nil
verilog-auto-input-ignore-regexp nil
verilog-auto-inst-column 40
verilog-auto-inst-dot-name nil
verilog-auto-inst-interfaced-ports nil
verilog-auto-inst-param-value nil
verilog-auto-inst-sort nil
verilog-auto-inst-template-numbers nil
verilog-auto-inst-vector t
verilog-auto-lineup 'declarations
verilog-auto-newline t
verilog-auto-output-ignore-regexp nil
verilog-auto-read-includes nil
verilog-auto-reset-blocking-in-non t
verilog-auto-reset-widths t
verilog-auto-save-policy nil
verilog-auto-sense-defines-constant nil
verilog-auto-sense-include-inputs nil
verilog-auto-star-expand t
verilog-auto-star-save nil
verilog-auto-template-warn-unused nil
verilog-auto-tieoff-declaration "wire"
verilog-auto-tieoff-ignore-regexp nil
verilog-auto-unused-ignore-regexp nil
verilog-auto-wire-type nil
verilog-before-auto-hook nil
verilog-before-delete-auto-hook nil
verilog-before-getopt-flags-hook nil
verilog-before-save-font-hook nil
verilog-cache-enabled t
verilog-case-fold t
verilog-case-indent 2
verilog-cexp-indent 2
verilog-compiler "echo 'No verilog-compiler set, see "M-x describe-variable verilog-compiler"'"
verilog-coverage "echo 'No verilog-coverage set, see "M-x describe-variable verilog-coverage"'"
verilog-delete-auto-hook nil
verilog-getopt-flags-hook nil
verilog-highlight-grouping-keywords nil
verilog-highlight-includes t
verilog-highlight-modules nil
verilog-highlight-p1800-keywords nil
verilog-highlight-translate-off nil
verilog-indent-begin-after-if t
verilog-indent-declaration-macros nil
verilog-indent-level 3
verilog-indent-level-behavioral 3
verilog-indent-level-declaration 3
verilog-indent-level-directive 1
verilog-indent-level-module 3
verilog-indent-lists t
verilog-library-directories '(".")
verilog-library-extensions '(".v" ".sv")
verilog-library-files nil
verilog-library-flags '("")
verilog-linter "echo 'No verilog-linter set, see "M-x describe-variable verilog-linter"'"
verilog-minimum-comment-distance 10
verilog-mode-hook 'verilog-set-compile-command
verilog-mode-release-emacs nil
verilog-mode-version "2017-07-14-c36a886-vpo"
verilog-preprocessor "vppreproc FLAGS FILE"
verilog-simulator "echo 'No verilog-simulator set, see "M-x describe-variable verilog-simulator"'"
verilog-tab-always-indent t
verilog-tab-to-comment nil
verilog-typedef-regexp nil
verilog-warn-fatal nil
)
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