module test (/*AUTOARG*/
    // Inputs
    i_blc, I_cdef
    ) ;
    input  i_blc, I_cdef;
    reg [par_a -1:0] b,c;
    
    always @ ( posedge CLK or negedge RSTN ) begin
       if(!RSTN) begin
          /*AUTORESET*/
          // Beginning of autoreset for uninitialized flops
          b = {par_a{1'b0}};
          c = {par_a{1'b0}};
          // End of automatics
       end
       else begin
          b=i_blc+I_cdef;
          c=b;
          
       end
    end
endmodule // test

</code>

module test (/*AUTOARG*/
              // Inputs
              i_blc, I_cdef
              ) ;
    input  i_blc, I_cdef;
    reg [par_a -1:0] b,c;
    
    always @ ( posedge CLK or negedge RSTN ) begin
       if(!RSTN) begin
          /*AUTORESET*/
          // Beginning of autoreset for uninitialized flops
          b = {par_a{1'b0}};
       c = {par_a{1'b0}};      // error indent
       // End of automatics    // error indent
    end                        // error indent
       else begin              // OK
          b=i_blc+I_cdef;
          c=b;
          
       end
    end
endmodule // test
</code>

Emacs  : GNU Emacs 24.5.1 (i686-pc-mingw32)
 of 2015-04-11 on LEG570
Package: verilog-mode v2017-07-14-c36a886-vpo

current state:
==============
(setq
 verilog-active-low-regexp nil
 verilog-after-save-font-hook nil
 verilog-align-ifelse nil
 verilog-assignment-delay ""
 verilog-auto-arg-sort nil
 verilog-auto-declare-nettype nil
 verilog-auto-delete-trailing-whitespace nil
 verilog-auto-endcomments t
 verilog-auto-hook nil
 verilog-auto-ignore-concat nil
 verilog-auto-indent-on-newline t
 verilog-auto-inout-ignore-regexp nil
 verilog-auto-input-ignore-regexp nil
 verilog-auto-inst-column 40
 verilog-auto-inst-dot-name nil
 verilog-auto-inst-interfaced-ports nil
 verilog-auto-inst-param-value nil
 verilog-auto-inst-sort nil
 verilog-auto-inst-template-numbers nil
 verilog-auto-inst-vector t
 verilog-auto-lineup 'declarations
 verilog-auto-newline t
 verilog-auto-output-ignore-regexp nil
 verilog-auto-read-includes nil
 verilog-auto-reset-blocking-in-non t
 verilog-auto-reset-widths t
 verilog-auto-save-policy nil
 verilog-auto-sense-defines-constant nil
 verilog-auto-sense-include-inputs nil
 verilog-auto-star-expand t
 verilog-auto-star-save nil
 verilog-auto-template-warn-unused nil
 verilog-auto-tieoff-declaration "wire"
 verilog-auto-tieoff-ignore-regexp nil
 verilog-auto-unused-ignore-regexp nil
 verilog-auto-wire-type nil
 verilog-before-auto-hook nil
 verilog-before-delete-auto-hook nil
 verilog-before-getopt-flags-hook nil
 verilog-before-save-font-hook nil
 verilog-cache-enabled t
 verilog-case-fold t
 verilog-case-indent 2
 verilog-cexp-indent 2
 verilog-compiler "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
 verilog-coverage "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
 verilog-delete-auto-hook nil
 verilog-getopt-flags-hook nil
 verilog-highlight-grouping-keywords nil
 verilog-highlight-includes t
 verilog-highlight-modules nil
 verilog-highlight-p1800-keywords nil
 verilog-highlight-translate-off nil
 verilog-indent-begin-after-if t
 verilog-indent-declaration-macros nil
 verilog-indent-level 3
 verilog-indent-level-behavioral 3
 verilog-indent-level-declaration 3
 verilog-indent-level-directive 1
 verilog-indent-level-module 3
 verilog-indent-lists t
 verilog-library-directories '(".")
 verilog-library-extensions '(".v" ".sv")
 verilog-library-files nil
 verilog-library-flags '("")
 verilog-linter "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
 verilog-minimum-comment-distance 10
 verilog-mode-hook 'verilog-set-compile-command
 verilog-mode-release-emacs nil
 verilog-mode-version "2017-07-14-c36a886-vpo"
 verilog-preprocessor "vppreproc __FLAGS__ __FILE__"
 verilog-simulator "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
 verilog-tab-always-indent t
 verilog-tab-to-comment nil
 verilog-typedef-regexp nil
 verilog-warn-fatal nil
 )

modified   verilog-mode.el
@@ -6426,7 +6426,7 @@ Return >0 for nested struct."
                         (equal (char-before) ?\;)
                         (equal (char-before) ?\}))
                     ;; skip what looks like bus repetition operator {#{
-                   (not (string-match "^{\\s-*[0-9]+\\s-*{" (buffer-substring p (point)))))))))
+                   (not (string-match "^{\\s-*[0-9a-zA-Z_]+\\s-*{" (buffer-substring p (point)))))))))
        (progn
          (let ( (pt (point)) (pass 0))
            (verilog-backward-ws&directives)