Author Name: Maciej Piechotka
Original Redmine Issue: 1189 from https://www.veripool.org

Currently the Verilog can be compiled in a way that ignores the parameters as compile-time constructs. That makes testing generic components harder as I cannot just parametrize test to test edge cases for IP block.

It would be nice if verilog could compile code to templated class:

module(clk, out);
     parameter WIDTH = 32;
     parameter MAX = 64;
     input bit clk;
     output bit [WIDTH-1:0] out;
     initial out = 0;
     always_ff @(posedge clk) begin
         out <= (out == MAX - 1) ? 0 : out + 1;
     end
endmodule

Would compile to:

template<size_t WIDTH = 32, size_t MAX = 64>
VL_MODULE(...) {
     // ...
};

(This is an example - using functions would require using C++ constexpr functions or something similar)