Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Can't override parameter defined as "type xxxx" through command line with "-G" #1192

Closed
veripoolbot opened this issue Aug 25, 2017 · 6 comments
Labels
resolution: wontfix Closed; work won't continue on an issue or pull request type: feature-IEEE Request to add new feature, described in IEEE 1800

Comments

@veripoolbot
Copy link
Contributor


Author Name: Enzo Chi
Original Redmine Issue: 1192 from https://www.veripool.org


Verilator support type as parameter as "parameter type DATA_T = byte" but can't override it from command line with "-G"

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Enzo Chi
Original Date: 2017-08-25T02:01:28Z


I have a simple test file:

module dummy #(parameter type DATA_T = byte)
(
input DATA_T din,
output DATA_T dout
);

 assign dout = din + 1'b1;

endmodule // dummy

It can be compiled as: verilator --cc dummy.sv
But report error when: verilator --cc dummy.sv -GDATA_T=int

Error message:

%Error: Parameters from the command line were not found in the design: DATA_T

%Error: Command Failed verilator/3_906/bin/verilator_bin --cc dummy.sv '-GDATA_T=byte'

Verilator Version: 3.906

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-08-29T02:56:25Z


This is slightly painful to fix as the parser is all that understands the types, not the command line parser. Would this be OK to only work for simple built in non-sized types ("int" etc)? Any idea if it works with other simulators?

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Enzo Chi
Original Date: 2017-08-29T11:02:11Z


I don't have other simulator with me. I may try it later on the edaplayground.com

Only support simple built in non-sized types will not be good enough for me. Because I would expect to pass different type of packed structs here (or logic vector which synthesis tool supports).

I am not good at software, about the parser issue, I can understand, but is it possible to do something like just replace the original type with override one to temporary files and the parse them.

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-08-29T12:33:57Z


The simplest thing would be to do this:

ifndef PARAM_TYPE define PARAM_TYPE logic
endif parameter type foo_t = PARAM_TYPE;

Then use -DPARAM_TYPE=int.

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-08-29T12:36:36Z


And if you can't edit the source, Verilog-Mode can easily make a wrapper you then edit.

module ModnameStub (/AUTOARG/);
/AUTOINOUTPARAM("Modname")/
/AUTOINOUTMODULE("Modname")/
/AUTOWIRE/
Modname sub (.*);
endmodule

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-11-18T22:56:38Z


As far as I can tell this isn't supported in other simulators, so unless someone wants to commit a relatively complicated patch, the best bet is the `ifdef trick mentioned earlier.

@veripoolbot veripoolbot added resolution: wontfix Closed; work won't continue on an issue or pull request type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
resolution: wontfix Closed; work won't continue on an issue or pull request type: feature-IEEE Request to add new feature, described in IEEE 1800
Projects
None yet
Development

No branches or pull requests

1 participant