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Can't override parameter defined as "type xxxx" through command line with "-G" #1192
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Original Redmine Comment I have a simple test file: module dummy #(parameter type DATA_T = byte)
endmodule // dummy It can be compiled as: verilator --cc dummy.sv Error message: %Error: Parameters from the command line were not found in the design: DATA_T %Error: Command Failed verilator/3_906/bin/verilator_bin --cc dummy.sv '-GDATA_T=byte' Verilator Version: 3.906 |
Original Redmine Comment This is slightly painful to fix as the parser is all that understands the types, not the command line parser. Would this be OK to only work for simple built in non-sized types ("int" etc)? Any idea if it works with other simulators? |
Original Redmine Comment I don't have other simulator with me. I may try it later on the edaplayground.com Only support simple built in non-sized types will not be good enough for me. Because I would expect to pass different type of packed structs here (or logic vector which synthesis tool supports). I am not good at software, about the parser issue, I can understand, but is it possible to do something like just replace the original type with override one to temporary files and the parse them. |
Original Redmine Comment The simplest thing would be to do this:
Then use -DPARAM_TYPE=int. |
Original Redmine Comment And if you can't edit the source, Verilog-Mode can easily make a wrapper you then edit. module ModnameStub (/AUTOARG/); |
Original Redmine Comment As far as I can tell this isn't supported in other simulators, so unless someone wants to commit a relatively complicated patch, the best bet is the `ifdef trick mentioned earlier. |
Author Name: Enzo Chi
Original Redmine Issue: 1192 from https://www.veripool.org
Verilator support type as parameter as "parameter type DATA_T = byte" but can't override it from command line with "-G"
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