Feature request: Nested module definitions #1195
Labels
resolution: wontfix
Closed; work won't continue on an issue or pull request
type: feature-IEEE
Request to add new feature, described in IEEE 1800
Author Name: Rob Stoddard
Original Redmine Issue: 1195 from https://www.veripool.org
I have run into this issue where two modules with the same names can create a conflict. Since I'm dealing with a lot of NIH IP, the solution cannot be merely to "don't name two modules the same thing." I can however ensure that modules are scoped by nesting them inside of a module that wraps each IP in the design. To that end, the SystemVerilog feature of nested module definitions would be a very nice thing to have in Verilator. For example, I would like to be able to do this:
How hard would this be to add?
Thank you
Rob Stoddard
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