Author Name: Shinobu TAKANASHI
Original Redmine Issue: 1198 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

Hi,

I'd worked for 2 days to find out the way to "access signals in C" and noticed the document was wrong (for recent version of Verilator).

The following

cout << "clock is " << top->v->clk << endl;
</code>

should be like bellow, right?

cout << "clock is " << top->our->clk << endl;
</code>

I was just lucky I could find the clue:
openrisc/orpsoc-cores#111

Hope this will be fixed.

Thanks