(flycheck-define-checker my-verilog-verilator
     "A Verilog syntax checker using the Verilator Verilog HDL simulator.

See URL `https://www.veripool.org/wiki/verilator'.
The original checker(verilog-verilator) doesn't work, when start-process call the verilator, it return a message that "Exec format error",
for the reasion described above, use bash to start verilator can be OK
"
     :command ("sh" "verilator" "--lint-only" "-Wall" "-Wno-ASSIGNDLY" source)
     :error-patterns
     ((warning line-start "%Warning-" (zero-or-more not-newline) ": "
               (file-name) ":" line ": " (message) line-end)
      (error line-start "%Error: " (file-name) ":"
             line ": " (message) line-end))
     :modes verilog-mode)
</code>