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Can't get Verilog::Netlist::Net object from Pin for partial vector #1201
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Original Redmine Comment Leon Medpum wrote:
@wilson: However, the netnames function does not really make sense as is IMHO. I kinda lost track about who proposed which parts of the API but I guess the netnames function is a potpourri of both our ideas and the outcome is probably not what either of us wanted. :) As is the nets function is a bad copy of the pinselects function with the disadvantage of returning untyped hashes similar to Verilog::Netlist::PinSelection. KR, Stefan |
Original Redmine Comment The net2[0] is legal verilog. I agree the net is not 'net2' it is actually 'net2[0]' The '' and space at the end make the special characters part of the net. Our verilog has a lot of crazy syntax, and I'm testing out different corner cases. I don't think I communictaed my problem well. Here is the test program I used:
The result looks like:
For CellName=submod1 this is exactly what i expect. For CellName=submod2, the 'NetName' is empty which is not what I expect. |
Original Redmine Comment After looking at it further, I don't understand why your code seems to misdetect the net[0] and correctly handles the net4[], whereas mine is the reverse... |
Original Redmine Comment On further follow up, this is due to the 'use_pinselects => 1' option. I do noty understand why the behavior changes when using this option. |
Original Redmine Comment Leon Medpum wrote:
No, @net2[0]@ is not valid (but that's not what you wrote initially anyway ;)
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Original Redmine Comment Leon Medpum wrote:
Because this option was added to parse the LSB/MSB syntax. Previously this was not covered at all in Verilog-Perl and the identifiers were not really distinguished from the indices at all. |
Original Redmine Comment Sorry, I don't know how to display the bus notation in this form without the pre tags. The backslash was just so it wouldn't superscript. Thank you for identifying the typo in my verilog, agreed that is not supposed to work. Since the pinselect objects are created with and without the use_pinselect option, I hadn't realized it changed the behavior in this way. Thank you for your help. Feel free to close this issue. |
Original Redmine Comment hello all , can u please tell me what is this Opt->libext(".sv") doing here? |
Original Redmine Comment Your libext post seems unrelated to this issue, in the future please make a new issue or forum post. But anyways the libext setting is the same as +libext+.sv passed to your simulator, used to resolve module names to filenames. Or, just pass every filename needed through the command line (e.g. to read_file). |
Author Name: Leon Medpum
Original Redmine Issue: 1201 from https://www.veripool.org
using git version: 5f176d4
I have the following Verilog:
If (after linking) I query the pins for submod2, I query the pins for cell submod2, I see net4a and net5. If I query the pinselects() for each pin, I see respectively 'net4[2:1]' and 'net4[0]', but if i query the nets() for net4a or net5, I do not get any results. The PinSelection object does not provide any mechanism to locate the Verilog::Netlist::Net object. What is the recommended method to trace the connectivity? I thought this was the purpose of the msb/lsb attributes of the array returned by Verilog::Netlist::Pin->nets()
As a side note, the nets() fundtion works fine when tracing the connectivity through submod1
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