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Don't warn about little endian ordering for arrays of cells #1202
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Original Redmine Comment Checking for a back of cell doesn't seem quite right, but perhaps. Can you please update your patch to include/modify a test case, thanks. |
Original Redmine Comment Update with minimal test. Without my change the test fails with the previously mentioned little endian warning. With my change it does not. |
Original Redmine Comment I played a hunch and see a real bug, if you connect a e.g. 5 bit signal like this
Then verilator wires the bits backwards (although it seems so does one commercial simulator, while another gets it right.) I'll fix that too. This however brings up an important point, in the above usage it seems non-obvious that the bits connect backwards and the littleendian warning does seem appropriate. I'm pretty sure if I poll some coworkers they'll be surprised this is how it correctly connects. It's much better to write
so I'm inclined to fix the connection issue but leave the message enabled. What do you think? |
Original Redmine Comment Hmm, interesting. I think what I would ideally want is for Verilator to warn me when connecting signals like that in a way that they would be reversed. We use arrays of interfaces quite often, but it's very rare for us to use that feature where a signal is spread out among all of the instances. That's a more involved change though, so if you want to just close this issue out that's fine with me |
Original Redmine Comment Warning suppressed only when it shouldn't matter. Pushed to git towards 3.911. |
Original Redmine Comment In 3.912. |
Author Name: Mike Popoloski
Original Redmine Issue: 1202 from https://www.veripool.org
If you declare an array of instances (like say, interfaces) you will pretty much always get a warning about how it's in little endian order even though that makes no sense. I've attached a proposed fix that we've been running with locally.
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