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Allow modules port parameters to not have a default in their declaration #1213

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veripoolbot opened this issue Sep 14, 2017 · 2 comments
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Allow modules port parameters to not have a default in their declaration #1213

veripoolbot opened this issue Sep 14, 2017 · 2 comments
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Mike Popoloski
Original Redmine Issue: 1213 from https://www.veripool.org

Original Assignee: Mike Popoloski

SystemVerilog allows module port parameters to not have defaults, which forces you to provide a value at instantiation time. This mostly just requires a minor grammar change.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-09-15T01:20:53Z

Great again, thanks for adding the negative test too.

Pushed to git towards 3.911.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-09-23T14:14:15Z

In 3.912.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
@wsnyder wsnyder mentioned this issue May 3, 2020
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
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