define macro including
", \
", and `` has issues for empty strings
#1225
Labels
resolution: fixed
Closed; fixed
Author Name: Odd Magne Reitan
Original Redmine Issue: 1225 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
Run code at bottom as verilator -E -P test.sv
ITEM(CPU,)); should produce "CPU" but, the macro expansion leaves 3 "
" characters which verilator has problem with and issues:%Error: test.sv:35: `" not terminated at EOF
%Error: Internal Error: test.sv:35: ../V3PreProc.cpp:1207: Bad case
Synopsys VCS and Cadence Incisive correctly outputs "CPU" in this case.
As it is defined, but to an empty text, it shoudl output "XILINX_".
Note in particular that issue 1 is not solved by adding white-spaces like $display(`ITEM(CPU, ));
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