Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Issue #1225

`define macro including `", `\`", and `` has issues for empty strings

Added by Odd Magne Reitan over 1 year ago. Updated over 1 year ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
TranslationError
% Done:

0%


Description

Run code at bottom as verilator -E -P test.sv

1. The intension is that $display(`ITEM); should produce "CPU" but, the macro expansion leaves 3 "`" characters which verilator has problem with and issues: %Error: test.sv:35: `" not terminated at EOF %Error: Internal Error: test.sv:35: ../V3PreProc.cpp:1207: Bad case

Synopsys VCS and Cadence Incisive correctly outputs "CPU" in this case.

2. Using `` to avoid space when concatenating a text to make up a define works in Verilator when FAMILY is defined to something - like the out-commented "Artix". However, if the string is empty it depends; if Newline after FAMILY it does not output the expected "XILINX_", but it does if some one or more space characters are added before newline.

As it is defined, but to an empty text, it shoudl output "XILINX_".

Note in particular that issue 1 is not solved by adding white-spaces like $display(`ITEM);

`define ITEM(SUB,UNIT) `STRING(SUB``UNIT)

module test ();
`define STRING( A ) `"A`" 

//`define FAMILY Artix
`define FAMILY

 `define XILINX_```FAMILY

  initial
    begin
      $display(`ITEM(RAM,0));
      $display(`ITEM(CPU,));

`ifdef XILINX_Artix
      $display("XILINX_Artix is defined");
`endif      
`ifdef XILINX_
      $display("XILINX_ is defined");
`endif      
`ifdef XILINX_FAMILY
      $display("XILINX_FAMILY is defined");
`endif      
    end // initial begin

endmodule // test

History

#1 Updated by Odd Magne Reitan over 1 year ago

A more interesting special-case of issue 2 is the code below. Run as verilator -E -P test.sv and it will output

%Error: test.sv:12: Expecting symbol to terminate ``; whitespace etc cannot follow ``. Found: EOF %Error: Exiting due to 1 error(s)

Note: Adding a module or something removes this error; that is why it was not visible in the original testcase. Typically `defines are contained within a file which is listed in a manifest file sourced by the -F option. The issue is also visible then.

a) For a parser, `` is followd by something else than whitespace; `FAMILY. Hence, the error message is not right. That `FAMILY expands to whitespace or CR is a different story. b) No CAD tools seems to have a problem with this construct. c) Problem exist if FAMILY is either undefined or defined to nothing.

//`define FAMILY Artix
//`define FAMILY

`ifdef FAMILY
 `define XILINX_```FAMILY
`endif

#2 Updated by Wilson Snyder over 1 year ago

  • Category set to TranslationError
  • Status changed from New to Resolved
  • Assignee set to Wilson Snyder

Thanks for the good report & test.

Fixed in git towards 3.914.

Matching bug in Verilog-Perl, fixed in git towards 3.446.

Please give it a try to make sure there's not another missing case (had similar issue with "`foo```bar(param)" )

#3 Updated by Wilson Snyder over 1 year ago

  • Status changed from Resolved to Closed

In 3.914.

Also available in: Atom