Author Name: Odd Magne Reitan
Original Redmine Issue: 1226 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

In a verilog project, common structures like defines, macro functions, system verilog functions and tasks may be contained within one or more include files. Any file that makes use these common structures include the include file. A common way to ensure the definitions take place only once is to include in the top of the include file:

`ifndef INC1
 `define INC1
.. <Content to be defined only once>
`endif

However, if the same include file is included from different files, it seems like verilator in precompile mode (-E option) forget the `define INC1 and includes the content of inc1.sv also second time.
Run
verilator -E -P -F test.mft
Output is

module dummy ();
  initial
     $display("This should occur only once");
endmodule  
module dummy ();
  initial
     $display("This should occur only once");
endmodule  

This duplication will (dependent of the content of the include file) lead to error if the precompiled output file is simulated in a simulator. If the include file is included twice or more from within the same file, the module "dummy" will be included only once as expected.