Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-10-18T20:55:11Z

I think it's getting mistaken for a constraint. Might you be able to try a fix? Here's another

module test_dummy_concat;

    always @(posedge clk or posedge reset)
      begin
         if (reset)
           begin
              counter <= {COUNTERBITS{1'b0}};
         out1 <= 1'b0;
         out2 <= 1'b0;
      end
    end
endmodule

Original Redmine Comment
Author Name: David Rogoff
Original Date: 2017-10-18T21:00:57Z

Wilson Snyder wrote:

I think it's getting mistaken for a constraint. Might you be able to try a fix? Here's another

[...]

My elisp isn't nearly up for this!

Original Redmine Comment
Author Name: Alex Reed
Original Date: 2017-11-13T20:59:42Z

This commit fixes the test-case.

commit 377003e15853bb921c6e4717f8a517f8ebbce8b4
Author: Alex Reed <alex.reed@broadcom.com>
Date:   Mon Nov 13 14:49:09 2017

     Improve indention of begin/end near nested braces
     
     * verilog-mode (verilog-at-constraint-p):  begin/end are illegal inside
       constraint blocks, so use that knowledge to make smarter indentation
       decisions.

I'm not particularly happy with some of the code in this area. The function @verilog-at-constraint-p@ is pretty precarious (really, all of the constraint detection code is difficult, and it spans most of the indent code). I find that it's very easy to get stuck in infinite loops with minor changes in this area. I also notice a pretty deep/expensive code path that's called 2x per indentation, and certain portions are called increasingly more often as the number of @{}@ pairs increases in a statement. Something is awry, but more investigation will have to wait for another day...

yes, it still exists some issues in @verilog-at-constraint-p like this: @veripoolbot
counter <= {COUNTERBITS-1{1'b0}};
or:
counter <= {COUNTERBITS*2{1'b0}};
or
counter <= {COUNTERBITS/2{1'b0}};

yes, it still exists some issues in @verilog-at-constraint-p like this: @veripoolbot
counter <= {COUNTERBITS-1{1'b0}};
or:
counter <= {COUNTERBITS*2{1'b0}};
or
counter <= {COUNTERBITS/2{1'b0}};

@wsnyder