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Issue #1240

`" combined with `` in trouble if macro is not defined

Added by Odd Magne Reitan about 2 years ago. Updated about 2 years ago.

Status:
WillNotFix
Priority:
Normal
Assignee:
-
% Done:

0%


Description

Normaly, "vppreproc" or "verilator -P -E" is used to expand/decompile all macros. However, if one macro is not defined the macro name should be left as is because you can then define these macros in a new simulation of the resulting file. This is also usually the current behaviour.

However, consider the example below. Put it in a file and call it test.sv
 `define redef( NAME ) `ifdef NAME `undef NAME `endif

 `define MYLIST\
   `ITEM(        A0,    item)

 `define STRING( A ) `"A`" 

// Works if defined here
// `define ITEM_MYLIST_A0 A0

package test3_p;
  `redef(ITEM)        `define ITEM(        ID, TYPE) '{ `STRING(TYPE), `STRING(`ITEM_MYLIST_``ID) },
  typedef struct { string SimpleDefine; string ComplexDefine;} MYLIST_string_t[];
  MYLIST_string_t MYLIST_string =
  '{
    `MYLIST
    '{"",""} };
endpackage // test3_p

module test_module ();
  import test3_p::*;

  initial
    begin
      $display(MYLIST_string[0].SimpleDefine);
      $display(MYLIST_string[0].ComplexDefine);
    end

Running
verilator -P -E test.sv
or
vppreproc --noblank --noline test.sv
leads to
package test3_p;
  typedef struct { string SimpleDefine; string ComplexDefine;} MYLIST_string_t[];
  MYLIST_string_t MYLIST_string =
  '{
   '{ "item", `ITEM_MYLIST_A0"" },
    '{"",""} };
endpackage  
module test_module ();
  import test3_p::*;
  initial
    begin
      $display(MYLIST_string[0].SimpleDefine);
      $display(MYLIST_string[0].ComplexDefine);
    end
endmodule  

Note that `ITEM_MYLIST_A0"" in the correct behahviour should have been "`ITEM_MYLIST_A0".

Issue goes for verilator as well as vppreproc

Using Version 3.445 of vppreproc and verilator -version Verilator 3.915 devel rev verilator_3_914-11-g451483d

History

#1 Updated by Odd Magne Reitan about 2 years ago

Correction: It should be corrected to `"`ITEM_MYLIST_A0`" because the `" is necessary for the content to be interpreted as a macro.

#2 Updated by Odd Magne Reitan about 2 years ago

Correction to correction: Enclosing inside `" like "`ITEM_MYLIST_A0" does work in Synopsys VCS when the macro `ITEM_MYLIST_AO is defined. However, this is outside the SystemVerilog LRM, because the `" construct is just specified to be used within macro functions. And indeed, Cadence Incisive issues error for the construct.

A possible fix: If verilator/vppreproc discovers an undefined macro within a pair of `", verilator/vppreproc must define a macro function to keep all the content within the pair of `" inside a macro. The expanded module should then look like this - where vppreprocStr is a macro verilator/vppreproc creates for these kind of issues:

`define vppreprocStr( S ) `"S`" 

package test3_p;
  typedef struct { string SimpleDefine; string ComplexDefine;} MYLIST_string_t[];
  MYLIST_string_t MYLIST_string =
  '{
   '{ "item", `vppreprocStr(`ITEM_MYLIST_A0)  },
    '{"",""} };
endpackage // test3_p
module test_module ();
  import test3_p::*;
  initial
    begin
      $display(MYLIST_string[0].SimpleDefine);
      $display(MYLIST_string[0].ComplexDefine);
    end
endmodule // test_module

Keeping undefined macros during preprocessing so they can be defined later is a useful and nice feature. But I realize it becomes complex in such special situation where the macro occurs within a macro function.

#3 Updated by Wilson Snyder about 2 years ago

  • Status changed from New to WillNotFix

Sorry, I agree there's too many edge cases to make this work consistently, and it's impossible to fully solve as for example defines could specify preprocessor directives themselves that change later preprocessing (such as the name of an include file, but the simplest case is an ifdef changes behavior if you didn't properly make the define on the first pass.)

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