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Signal not driven/used warning when assigning values to modports #1241

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veripoolbot opened this issue Nov 6, 2017 · 4 comments
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area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed

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Author Name: Laurens van Dam
Original Redmine Issue: 1241 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Hi Verilator team,

I have observed certain behaviour with Verilator of which I am not sure if this intended or not.

I am using an interface with two modports to create a master/slave structure. I happen to get "Signal is not driven, nor used" warnings for signals of which I am certain that they are driven/used.

Attached is a small example where this behaviour occurs and illustrates the problem. I can suppress the warnings by adding lint_off tags, but I prefer not to do this every time. I do run verilator with the -Wwarn-style option, which also triggers these warnings.

The small design synthesizes fine and shows the correct behavior (without any non-driven signals).

I look forward to hearing your opinions about this.

Thanks,

Laurens

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Original Redmine Comment
Author Name: Todd Strader (@toddstrader)
Original Date: 2017-11-06T10:16:57Z


Your master modport's signal is an input, yet you are assigning it in your example module. Try swapping master and slave's directions.

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Original Redmine Comment
Author Name: Laurens van Dam
Original Date: 2017-11-07T13:14:40Z


Todd Strader wrote:

Your master modport's signal is an input, yet you are assigning it in your example module. Try swapping master and slave's directions.

Swapping directions does not get rid of the Verilator warnings. Attached are the new files. Synthesis in Vivado does not mention anything about non-driven/used signals.

%Warning-UNUSED: example_module.sv:11: Signal is not driven, nor used: dummy_in
%Warning-UNUSED: Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message.
%Warning-UNUSED: example_module.sv:12: Signal is not driven, nor used: dummy_out
%Error: Exiting due to 2 warning(s)
</code>

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-11-15T01:11:48Z


Fixed in git towards 3.915.

Also added error when modport inputs are assigned to.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-11-25T20:47:37Z


In 3.916.

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area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed
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