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I am encountering an issue where AUTOINST is declaring a vector with incorrect array bounds.
I have attached two files to illustrate the problem:
test_submodule.sv (this is the module being AUTOINST'ed)
test_top.sv (this is the top level design instantiating the submodule)
The issue is on line 57 of test_top.sv.
Here is what is produced by expanding AUTOs:
.b_tdata (a_tdata[B_WL-1:0]), // Templated
Here is what I expect to be produced based on the AUTO_TEMPLATE (note the array bounds of a_tdata):
.b_tdata (a_tdata[A_WL-1:0]), // Templated
I suspect the issue is triggered because test_submodule has a ports named a_tdata and b_tdata, but the AUTO_TEMPLATE is swapping them so port a_tdata is connected to signal b_tdata and port b_tdata is connected to signal a_tdata.
I tried the most recent version of verilog_mode.el (Nov 13, 2017).
Please take a look.
Thanks!
Clarke
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-11-15T00:47:54Z
The problem as you probably guessed is you're changing B_WL->A_WL, and another rule goes A_WL->B_WL.
So the code starts with your signal t_data[B_WL], then applies the first parameter change so has now t_data[A_WL] (properly), it then keeps going to the next parameter change and goes to t_data[B_WL] (incorrectly}.
You might think I could just stop on the first replacement, but then a case like "t_data[X_WL][Y_WL]" would not work with X_WL & Y_WL (non-swapped) being replaced.
I need to think if there's an easy way to do this, short of tokenizing the entire string and looking up every single token for replacements which would be a lot of code and slow.
Author Name: Clarke Watson
Original Redmine Issue: 1242 from https://www.veripool.org
Hi,
I am encountering an issue where AUTOINST is declaring a vector with incorrect array bounds.
I have attached two files to illustrate the problem:
The issue is on line 57 of test_top.sv.
Here is what is produced by expanding AUTOs:
.b_tdata (a_tdata[B_WL-1:0]), // Templated
Here is what I expect to be produced based on the AUTO_TEMPLATE (note the array bounds of a_tdata):
.b_tdata (a_tdata[A_WL-1:0]), // Templated
I suspect the issue is triggered because test_submodule has a ports named a_tdata and b_tdata, but the AUTO_TEMPLATE is swapping them so port a_tdata is connected to signal b_tdata and port b_tdata is connected to signal a_tdata.
I tried the most recent version of verilog_mode.el (Nov 13, 2017).
Please take a look.
Thanks!
Clarke
The text was updated successfully, but these errors were encountered: