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Issue #1244

V3Split not splitting

Added by John Coiner about 1 year ago. Updated 3 months ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
Performance
% Done:

0%


Description

We have an input like this:

always @(posedge clk) begin if ((rst_l == 0)) begin reg1 <= 1'b0; reg2 <= 1'b0; // ... snip ... reg10000 <= 1'b0; end else begin reg1 <= new_reg1; reg2 <= new_reg2; // ... snip ... reg10000 <= new_reg10000; end end

Essentially, it's thousands of resettable flops combined into a single always block.

It would be nice if V3Split were smart enough to split this up. There are a few bad consequences of not splitting this up:

  • It's bad for V3Gate runtime. We don't know why yet. Wilson saw V3Gate run orders of magnitude faster with the block split up.
  • It's bad for serial code scheduling. The code scheduler has no ability to reorder anything within this always block relative to anything else in the block. That's bad for dcaches, it limits verilator's ability to locate writes and reads of the same variable in close proximity.
  • (On the threads-jcoiner branch) It's bad for the thread partitioner's runtime, which degrades when some nodes in the graph have a huge number of dependency edges, as this one will.
  • (On the threads-jcoiner branch) It's bad for the output of the thread partitioner. We should have 10000 items that are trivially parallelizable, but instead we get a single atom that the partitioner cannot extract any parallelism from. This becomes a bottleneck on the final partitioned graph.

What exactly V3Split should output for this case is TBD. We probably don't want to reference the reset signal inline with every assignment (that's more instructions to run, and also more instructions to store.) We might want to break this large always block into a several medium-size always blocks, each of which evaluates the condition once, so that total code size and cpu footprint won't grow much.

History

#1 Updated by John Coiner about 1 year ago

Whoops, here's the above code sample with formatting:

always @(posedge clk) begin
  if ((rst_l == 0)) begin
    reg1 <= 1'b0;
    reg2 <= 1'b0;
    // ... snip ...
    reg10000 <= 1'b0;
  end
  else begin
    reg1 <= new_reg1;
    reg2 <= new_reg2;
     // ... snip ...
    reg10000 <= new_reg10000; end
end

#2 Updated by Wilson Snyder about 1 year ago

  • Status changed from New to Confirmed

#3 Updated by Wilson Snyder about 1 year ago

Added some example tests, test_regress/t/t_alw_split_rst.v

#4 Updated by Wilson Snyder 10 months ago

  • Status changed from Confirmed to Resolved

John Coiner provided an excellent patch which is merged into git develop-v4 branch, towards version 4.000.

Thanks John!!

#5 Updated by Wilson Snyder 3 months ago

  • Status changed from Resolved to Closed

In 4.002.

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