Original Redmine Comment
Author Name: David Rogoff
Original Date: 2017-12-18T21:56:44Z

I found a thread with this example:

 .lp_cmd_\(.*\)      (@"(if (equal vl-dir \\"output\\") \\"\\" (concat vl-width \\"'b0\\"))"),

It is an ok work-around but I thought these was a way to have AUTOREGINPUT declare the signals and then have them assigned to zero.

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-12-21T00:53:21Z

I think your workaround is the only choice at present.

I thought there could be something added like an AUTORESET for signals that came from AUTOREGRESET, but it would be hard to know what not to reset, you'd need a list, so I don't see that being more convenient than what the present templating gives you.

Original Redmine Comment
Author Name: David Rogoff
Original Date: 2017-12-26T21:47:24Z

Ack!

Well, this solution worked great - until it hit an input port that was multidimensional.

Now what?

Thanks & Happy New Year,

David

module a (input wire [15:0] md_input [4]); endmodule

module top;       
/* a AUTO_TEMPLATE (
  .\(.*\)    (@"(if (equal vl-dir \\"output\\") \\"\\" (concat vl-width \\"'b0\\"))"),
 );
 */
a inst_a
  (/*AUTOINST*/
    .md_input   (16'b0) // templated
   );
endmodule

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-12-26T23:33:53Z

If you're using non-SystemVerilog you'll need to assign manually. If using SV, the vl-width was unneeded and something like this might work (untested):

 /* a AUTO_TEMPLATE (
    .\(.*\)    (@"(if (equal vl-dir \\"output\\") \\"\\" (if vl-mbits \\"'{default:'0}\\" \\"'0\\"))"),
  );
  */

Original Redmine Comment
Author Name: David Rogoff
Original Date: 2017-12-27T00:02:56Z

Thanks for the super-fast reply! I hadn't thought of using pattern assignments. So close, but unfortunately, at least for Cadence, this gives a warning for ports that are single-bit scalars:

xmelab: *W,APSCXT (top.sv,300|62): Assignment pattern - scalar context is not legal [SystemVerilog].

Can the regex be modified to only work for multi-bit ports? Could vl-width be used? Would that work for an unpacked array of single bit:

output wire out_port_aa [4];

If so, then the previous regex could be modified to only run for scalar ports.

David

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-12-27T02:06:17Z

The intent of the "(if vl-mbits" was to only have it do that on memories, perhaps it needs some tweaking.

Original Redmine Comment
Author Name: David Rogoff
Original Date: 2017-12-27T22:39:02Z

I did some more experiments and it looks like vl-mbits doesn't work right.

Here's my template and used variables to make it readable:

(setq my-nc-output "/NC/")
(setq my-nc-input-scalar "1'b0")
(setq my-nc-input-vector "'0")
(setq my-nc-input-mdv "'{default:'0}")
(setq my-space "|")

.(.*) (@" (concat (if (equal vl-dir \"output\") my-nc-output (if (equal vl-bits \"\") my-nc-input-vector my-nc-input-mdv) ) my-space vl-width my-space vl-bits my-space vl-mbits ) "),

To debug, I used this template that just prints the variable values:

 .\(.*\)    (@" (concat my-space vl-width my-space vl-bits my-space vl-mbits my-space  )  "),

Here are the port declarations followed by the results of AUTO:

input wire [8:0] mixed_mda_var [2],
.mixed_mda_var (|9|[8:0]||), // Templated

input wire unpacked_scalar_var [2],
.unpacked_scalar_var (|1|||), // Templated

input wire scalar_var,
.scalar_var (|1|||), // Templated

input wire [1:0] packed_vec_var,
.packed_vec_var (|2|[1:0]||), // Templated

So, vl-mbits is always null. And, there's no other way to identify a 1-bit scalar vs an unpacked array of 1-bit scalars (2nd and 3rd cases).

David

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-01-02T15:12:25Z

I think this works:

      /* sub AUTO_TEMPLATE (
        .\(.*\)    (@"(concat (if (equal vl-dir \\"output\\") my-nc-output  (if (not vl-memory) my-nc-input-vector  my-nc-input-mdv) ) )"),
         ) */

Is there a way to tie off 0 for all the unused input, at the meanwhile leave all unused output as dangling?

I just want to keep this coding style as:
.unused_input ( {32{1'b0}} ),
.unused_output (),

I updated the FAQ with this:

https://www.veripool.org/projects/verilog-mode/wiki/Faq#how-do-i-use-auto_template-to-tie-off-inputs-to-zero