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modport declaration incorrectly treats some outputs as inputs #1246

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veripoolbot opened this issue Nov 28, 2017 · 2 comments
Closed

modport declaration incorrectly treats some outputs as inputs #1246

veripoolbot opened this issue Nov 28, 2017 · 2 comments
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area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed

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@veripoolbot
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Author Name: Jeff Bush (@jbush001)
Original Redmine Issue: 1246 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


If you have define multiple outputs in a list within a modport, the first is treated as an output, but subsequent items are not, which (due to fix for bug 1110), causes it to erroneously flag an error. For example, given this:

modport master(output a, b);

a would be marked as an output, but b would not and would flag an error if someone attempted to assign a value to it. I'd expect b to be also treated as an output.

I've attached a test case that reproduces the issue.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-11-29T00:14:43Z


Simple enough fix, thanks for a complete test case.

Fixed in git towards 3.917.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-01-02T23:15:25Z


In 3.918.

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Labels
area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed
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