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When a parent module instantiates an interface (or passes an interface from its parent) to a child module, nested interface references are not found if the child and parent modules do not use the same port name for the interface reference. The following is a somewhat minimal reproduction of the problem:
%Error: mod1.sv:11: Can't find definition of 'foo' in dotted signal: foo.a.s1
%Error: Known scopes under 's1': <no cells found>
%Error: Internal Error: mod1.sv:11: ../V3Const.cpp:1531: Not linked
%Error: Command Failed /Users/arjen/dev/verilator/bin/verilator_bin -cc --trace --compiler clang -sv +1800-2012ext+sv -y . top.sv
Compilation succeeds if the offending line is commented out, or if all occurrences of "foo" in mod1 are replaced with if2_0. Please advice if this is expected and I am simply trying to do something that is not supported.
The text was updated successfully, but these errors were encountered:
Author Name: Arjen Roodselaar
Original Redmine Issue: 1250 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
When a parent module instantiates an interface (or passes an interface from its parent) to a child module, nested interface references are not found if the child and parent modules do not use the same port name for the interface reference. The following is a somewhat minimal reproduction of the problem:
This results in the following error:
Compilation succeeds if the offending line is commented out, or if all occurrences of "foo" in mod1 are replaced with if2_0. Please advice if this is expected and I am simply trying to do something that is not supported.
The text was updated successfully, but these errors were encountered: