//////////////////////////////////////////////////////////////////////////////
//  Copyright 2014 Dov Stamler (dov.stamler@gmail.com)
//
//  Licensed under the Apache License, Version 2.0 (the "License");
//  you may not use this file except in compliance with the License.
//  You may obtain a copy of the License at
interface wishbone_b3_if #(DAT_W  = 64, ADR_W  = 32, TAG_W  = 1) (input bit clk);

    localparam SEL_W = (DAT_W/8); // 1 select bit per data byte, divide by 8

    /// common signals ///
    logic [DAT_W-1:0] dat_i;  // data in bus
    logic [DAT_W-1:0] dat_o;  // data out bus
    logic             rst_i;  // core reset
    logic [TAG_W-1:0] tgd_i;  // tag for data in. Contains information associated to dat_i (such as parity).
    logic [TAG_W-1:0] tgd_o;  // tag for data out. Contains information associated to dat_o
endinterface: wishbone_b3_if



module dut
  #(
     parameter DAT_W = 16,
     parameter ADR_W = 16
     )
    (
     input logic clk,
     input logic rst,
     wishbone_b3_if #(.DAT_W(DAT_W), .ADR_W(ADR_W)) i_wishbone_b3_if,
     wishbone_b3_if i_wishbone_b3_if_not_param
     );
endmodule // dut



module tb_top;
    parameter ADR_W = 16;       // register bus address width
    parameter DAT_W = 16;       // register bus data width

    wishbone_b3_if #(.ADR_W(ADR_W),.DAT_W(DAT_W))  i_wishbone_b3_if           (clock);
    wishbone_b3_if                                 i_wishbone_b3_if_not_param (clock);

    dut
      #(/*AUTOINSTPARAM*/
        // Parameters
        .DAT_W						    (DAT_W),
        .ADR_W						    (ADR_W))
       dut
       (/*AUTOINST*/
        // Interfaces
        .i_wishbone_b3_if_not_param			    (i_wishbone_b3_if_not_param),
        // Inputs
        .clk						    (clk),
        .rst						    (rst),
        .wishbone_b3_if					    (wishbone_b3_if),
        .DAT_W						    (DAT_W),
        .ADR_W						    (ADR_W),
        .i_wishbone_b3_if				    (i_wishbone_b3_if));
endmodule // tb_top