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Author Name: Alex Solomatnikov Original Redmine Issue: 1254 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
Verilog:
forever begin #ifndef VERILATOR @(posedge clock) trace_count += 64'd1; #endif end
C:
while (1) { }
It would be better to error out.
The text was updated successfully, but these errors were encountered:
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2017-12-27T02:35:23Z
Reasonable enough, added to git towards 3.917.
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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2018-01-02T23:15:09Z
In 3.918.
wsnyder
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Author Name: Alex Solomatnikov
Original Redmine Issue: 1254 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
Verilog:
C:
It would be better to error out.
The text was updated successfully, but these errors were encountered: