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Issue #1254

verilator generates infinite loop

Added by Alex Solomatnikov over 1 year ago. Updated over 1 year ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
Lint
% Done:

0%


Description

Verilog:

    forever begin
#ifndef VERILATOR
      @(posedge clock) trace_count += 64'd1;
#endif
    end

C:

while (1) {
}

It would be better to error out.

History

#1 Updated by Wilson Snyder over 1 year ago

  • Category set to Lint
  • Status changed from New to Resolved
  • Assignee set to Wilson Snyder

Reasonable enough, added to git towards 3.917.

#2 Updated by Wilson Snyder over 1 year ago

  • Status changed from Resolved to Closed

In 3.918.

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