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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-01-01T22:09:24Z
If someone wants to take it on that would be great. Otherwise it's unlikely especially as there's already some bug backlog with the existing pretty functions.
Original Redmine Comment
Author Name: Don Pearce
Original Date: 2018-02-03T00:32:26Z
Another nice to have would be to align end of line comments in module header.
module foo
(
input rst_n, // My Reset
input clk, // My Clock
input d, // My D-input
output q, // My Q-Output
);
The port name already aligns properly ... but it would sure be nice to have it auto-beautify to:
module foo
(
input rst_n, // My Reset
input clk, // My Clock
input d, // My D-input
output q, // My Q-Output
);
Author Name: David Rogoff
Original Redmine Message: 2453 from https://www.veripool.org
Hi.
Would it be easy to make verilog-pretty-expr work for assign statements?
e.g.
assign a = 5;
assign long_name = a;
assign sig_b = a + 5;
Thanks,
David
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