Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Question: C-c = / verilog-pretty-expr work for assigns? #1256

Closed
veripoolbot opened this issue Dec 28, 2017 · 3 comments
Closed

Question: C-c = / verilog-pretty-expr work for assigns? #1256

veripoolbot opened this issue Dec 28, 2017 · 3 comments
Labels

Comments

@veripoolbot
Copy link
Collaborator


Author Name: David Rogoff
Original Redmine Message: 2453 from https://www.veripool.org


Hi.

Would it be easy to make verilog-pretty-expr work for assign statements?

e.g.

assign a = 5;
assign long_name = a;
assign sig_b = a + 5;

Thanks,

David

@veripoolbot
Copy link
Collaborator Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-01-01T22:09:24Z


If someone wants to take it on that would be great. Otherwise it's unlikely especially as there's already some bug backlog with the existing pretty functions.

@veripoolbot
Copy link
Collaborator Author


Original Redmine Comment
Author Name: David Rogoff
Original Date: 2018-01-01T22:21:46Z


Sure - I understand. I'm not very good at e-lisp but I'll take a look at verilog-pretty-expr and see if I can hack it :)

@veripoolbot
Copy link
Collaborator Author


Original Redmine Comment
Author Name: Don Pearce
Original Date: 2018-02-03T00:32:26Z


Another nice to have would be to align end of line comments in module header.

module foo
(
  input   rst_n, // My Reset
  input   clk, // My Clock
  input   d, // My D-input
 
  output  q, // My Q-Output
);

The port name already aligns properly ... but it would sure be nice to have it auto-beautify to:

module foo
(
  input   rst_n, // My Reset
  input   clk,   // My Clock
  input   d,     // My D-input
 
  output  q,     // My Q-Output
);

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
None yet
Development

No branches or pull requests

1 participant