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Issue #1257

Indentation within generate construct after always block is wrong if generate/endgenerate omitted

Added by Dan Hopper about 2 years ago. Updated 9 months ago.

Status:
Confirmed
Priority:
Normal
Assignee:
-
Category:
Indents
% Done:

0%


Description

There's an interesting difference in indentation in the below example module. The assign statement after an always block within a generate construct will be correctly indented if it's within a generate region (explicit generate/endgenerate lines), and incorrectly indented if the optional generate region (generate/endgenerate) is omitted.

If you load the below snippet in and reformat, the commented assign statement will be (incorrectly) indented to column 0. If you remove the comments on the generate/endgenerate pairs, it will indent properly. According to SV 1800-2012, the generate/endgenerate pair is optional, so ideally it would treat both versions identically.

I'm not proficient in Lisp so it wasn't immediately obvious to me how to fix the .el file to eliminate.

This occurs with verilog-mode-2017-12-21-39c77b2-vpo.el and also at least as far back as verilog-mode-842.el.

Thanks, Dan

module t1
 (
 );

genvar pipe;
logic [1:0] v;
logic x;

//generate
for (pipe=0; pipe<2; pipe++) begin : v_bl
    always_comb begin
        assign v[pipe] = '0;
    end
    assign x = '0;  // will be incorrectly indented to column 0
end
//endgenerate

endmodule

History

#1 Updated by Wilson Snyder about 2 years ago

  • Status changed from New to Confirmed
  • Assignee deleted (Wilson Snyder)

Seems so. The indentation code is generally maintained by patches, so if you could contribute a fix that would be great, otherwise it might be a while before it is fixed.

#2 Updated by David Rogoff 9 months ago

I just hit this. What's really weird is if I have the same generate loop twice but have another one in the middle with generate/endgenerate, the first loop will be messed up but the 2nd, identical copy will be indented correctly!

So, still no fix after a year? Wish my elisp skill was anywhere near good enough to help fix this.

David

module indent;

   // CASE 1 indented wrong.  See end of module
   for (genvar aa = 0; aa < FF; aa++) begin : gen_hh
      for (genvar bb = 0; bb < FF; bb++) begin : gen_ii
         if (`asdf [aa]) begin : gen_jj

            always_ff @ (negedge cc [aa][bb]) begin
               if (dd [aa][bb])) begin
                  for (uint_t d_idx = 0; d_idx < 16; d_idx++)
                    ee [aa][bb].push_front (tx_dfe_out [aa][bb]  [15 - d_idx]);
               end
            end

   always_ff @ (posedge hs_clk) begin
      ee_size [aa][bb] = ee [aa][bb].size();
      if (ee_size [aa][bb] > 0)
        gg [aa][bb] <= ee [aa][bb].pop_front;
   end

end : gen_jj
      end : gen_ii
   end : gen_hh

   // this indents correctly without generate/endgenerate
   for (genvar aa = 0; aa < FF; aa++) begin : gen_hh
      for (genvar bb = 0; bb < FF; bb++) begin : gen_ii
         if (`asdf [aa]) begin : gen_jj
            assign a[aa][bb] = aa + bb;
            assign b[aa][bb] = aa + bb;
         end : gen_jj
      end : gen_ii
   end : gen_hh

   // this works now with gen/endgen
   generate
      for (genvar aa = 0; aa < FF; aa++) begin : gen_hh
         for (genvar bb = 0; bb < FF; bb++) begin : gen_ii
            always @ (negedge cc)
              a = 5;
            always @ (negedge dd)
              w = 2;
         end : gen_ii
      end : gen_hh
   endgenerate

   // CASE 1 again. No change but works - apparently since verilog-mode hit a generate statement above this line
   for (genvar aa = 0; aa < FF; aa++) begin : gen_hh
      for (genvar bb = 0; bb < FF; bb++) begin : gen_ii
         if (`asdf [aa]) begin : gen_jj

            always_ff @ (negedge cc [aa][bb]) begin
               if (dd [aa][bb])) begin
                  for (uint_t d_idx = 0; d_idx < 16; d_idx++)
                    ee [aa][bb].push_front (tx_dfe_out [aa][bb]  [15 - d_idx]);
               end
            end

            always_ff @ (posedge hs_clk) begin
               ee_size [aa][bb] = ee [aa][bb].size();
               if (ee_size [aa][bb] > 0)
                 gg [aa][bb] <= ee [aa][bb].pop_front;
            end

         end : gen_jj
      end : gen_ii
   end : gen_hh

endmodule : indent

#3 Updated by David Rogoff 9 months ago

Even stranger - If I just put

   generate
   endgenerate

near the top of my module, everything after is indented correctly.

Good work-around for now and maybe good clue for finding the verilog-mode problem!

David

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