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I am having an issue with my behavioural SRAM model:
module sram #(
int unsigned DATA_WIDTH = 64,
int unsigned NUM_WORDS = 1024
)(
input logic clk_i,
input logic req_i,
input logic we_i,
input logic [$clog2(NUM_WORDS)-1:0] addr_i,
input logic [DATA_WIDTH-1:0] wdata_i,
input logic [DATA_WIDTH-1:0] be_i,
output logic [DATA_WIDTH-1:0] rdata_o
);
localparam ADDR_WIDTH = $clog2(NUM_WORDS);
logic [DATA_WIDTH-1:0] ram [NUM_WORDS-1:0];
logic [ADDR_WIDTH-1:0] raddr_q;
always_ff @(posedge clk_i) begin
if (req_i) begin
if (!we_i)
raddr_q <= addr_i;
else
for (int i = 0; i < DATA_WIDTH; i++)
if (be_i[i]) ram[addr_i][i] <= wdata_i[i];
end
end
assign rdata_o = ram[raddr_q];
endmodule
</code>
The interesting thing: When compiling with default parameter values e.g.: 64-bit and below everything works fine. When increasing the loop count to 65 and above I am getting
Error-BLKLOOPINIT: src/util/behav_sram.sv:42: Unsupported: Delayed assignment to array inside for loops (non-delayed is ok - see docs)
</code>
which seems to suggest that something is incorrect with the loop unrolling. It seems to be quite an artificial limitation that is the reason why I am posting here.
Thanks, Florian
The text was updated successfully, but these errors were encountered:
Author Name: Florian Zaruba (@zarubaf)
Original Redmine Issue: 1266 from https://www.veripool.org
Hi,
I am having an issue with my behavioural SRAM model:
The interesting thing: When compiling with default parameter values e.g.: 64-bit and below everything works fine. When increasing the loop count to 65 and above I am getting
which seems to suggest that something is incorrect with the loop unrolling. It seems to be quite an artificial limitation that is the reason why I am posting here.
Thanks, Florian
The text was updated successfully, but these errors were encountered: