%Error: Internal Error: /home/work/gitmodelsim/sim_lib/220model.v:3009: ../V3Tristate.cpp:1123: Unlinked
%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed /home/extssd/git/verilator//bin/verilator_bin -Wall +1364-2001ext+v --cc /home/work/gitmodelsim/sim_lib/220model.v --top-module lpm_mult --exe lpm_mult.cpp
</code>

module lpm_mult (
     dataa,  // Multiplicand. (Required)
     datab,  // Multiplier. (Required)
     sum,    // Partial sum.
     aclr,   // Asynchronous clear for pipelined usage.
     sclr,   // Synchronous clear for pipelined usage.
     clock,  // Clock for pipelined usage.
     clken,  // Clock enable for pipelined usage.
     result  // result = dataa[] * datab[] + sum. The product LSB is aligned with the sum LSB.
);

// GLOBAL PARAMETER DECLARATION
     parameter lpm_widtha = 1; // Width of the dataa[] port. (Required)
     parameter lpm_widthb = 1; // Width of the datab[] port. (Required)
     parameter lpm_widthp = 1; // Width of the result[] port. (Required)
     parameter lpm_widths = 1; // Width of the sum[] port. (Required)
     parameter lpm_representation  = "UNSIGNED"; // Type of multiplication performed
     parameter lpm_pipeline  = 0; // Number of clock cycles of latency
     parameter lpm_type = "lpm_mult";
     parameter lpm_hint = "UNUSED";

// INPUT PORT DECLARATION
     input  [lpm_widtha-1:0] dataa;
     input  [lpm_widthb-1:0] datab;
     input  [lpm_widths-1:0] sum;  =====================> here is the line 3009
     input  aclr;
     input  sclr;
     input  clock;
     input  clken;
...
</code>

- V3LinkDot.cpp:2191:    BEGIN 0x27a11b0 <e26718> {d3229} u1=0x295fcd0 [UNNAMED]
- V3LinkDot.cpp:2196:    cur=se0x295fcd0
- V3LinkDot.cpp:2200:    cur=se0x2967580
- V3LinkDot.cpp:2200:    cur=se0x296a6e0
- V3LinkDot.cpp:2200:    cur=se0x24e6b20
- V3LinkDot.cpp:1587:   MODULE 0x26ee430 <e69135> {d2985} u1=0x24d8d40 u4=0x1  TOP_lpm_mult  L1 [P]
- V3LinkDot.cpp:1632: (Backto) Link Cell: CELL 0x26f1620 <e69138> {d2985} u1=0x24e6b20  lpm_mult -> MODULE 0x2770dc0 <e69137> {d2985} u1=0x24e6b20 u4=0x1  lpm_mult  L2
%Error: Internal Error: /home/work/gitmodelsim/sim_lib/220model.v:3009: ../V3Tristate.cpp:1123: Unlinked
%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed /home/extssd/git/verilator//bin/verilator_bin -Wall +1364-2001ext+v --cc /home/work/gitmodelsim/sim_lib/220model.v --top-module lpm_mult --exe lpm_mult.cpp --debugi-V3LinkDot 9
</code>