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Issue #1269

Verilator supports assert but not assume

Added by Dan Gisselquist over 1 year ago. Updated over 1 year ago.

Status:
Closed
Priority:
Normal
Category:
Unsupported
% Done:

0%


Description

According to the 2004 Accellera specification, section 17.13.2 regarding the assume statement,

For simulation, the environment must be constrained such that the properties that are assumed shall hold. Like an assert property, an assumed property must be checked and reported if it fails to hold. There is no requirement on the tools to report successes of the assumed properties.

Judging by this statement, adding the "assume" capability into Verilator should be as simple as treating it just like the assert() statement. For this reason, I propose the following patch:

diff --git a/src/verilog.l b/src/verilog.l index c39a930..b1cee6a 100644 --- a/src/verilog.l +++ b/src/verilog.l @ -437,6 +437,7 @ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "always_comb" { FL; return yALWAYS_COMB; } "always_ff" { FL; return yALWAYS_FF; } "always_latch" { FL; return yALWAYS_LATCH; } + "assume" { FL; return yASSERT; } "assert" { FL; return yASSERT; } "bind" { FL; return yBIND; } "bit" { FL; return yBIT; }

assume.patch View (455 Bytes) Dan Gisselquist, 01/31/2018 01:37 AM

assume.patch View (3.13 KB) Dan Gisselquist, 01/31/2018 04:26 AM

History

#1 Updated by Dan Gisselquist over 1 year ago

That patch didn't come through properly. Here it is in code, and as an attached file.

diff --git a/src/verilog.l b/src/verilog.l
index c39a930..b1cee6a 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -437,6 +437,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "always_comb"        { FL; return yALWAYS_COMB; }
   "always_ff"        { FL; return yALWAYS_FF; }
   "always_latch"    { FL; return yALWAYS_LATCH; }
+  "assume"        { FL; return yASSERT; }
   "assert"        { FL; return yASSERT; }
   "bind"        { FL; return yBIND; }
   "bit"            { FL; return yBIT; }

Dan

#2 Updated by Wilson Snyder over 1 year ago

  • Status changed from New to Confirmed

Good point. The catch is if a user misuses the statement they might get errors like "Unexpected assert" instead of "Unexpected assume" which will be confusing.

So, would you mind making a new patch which returns yASSUME, then duplicate the verilog.y rules that use yASSERT to "or"-in yASSUME rules.

Also, please add a test case - you can duplicate a line in one of the existing test_regress tests.

Thanks.

#3 Updated by Dan Gisselquist over 1 year ago

Ok, sure and (hopefully) done. Please consider the attached (updated) patch,

Dan

#4 Updated by Wilson Snyder over 1 year ago

  • Category set to Unsupported
  • Status changed from Confirmed to Resolved
  • Assignee set to Dan Gisselquist

Perfect, thanks. Fixed in git towards 3.919.

#5 Updated by Wilson Snyder over 1 year ago

  • Status changed from Resolved to Closed

In 3.920.

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