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Issue #1276

vcd trace splits packed data type when it comes through a typedef

Added by Christopher Russell about 1 year ago. Updated 6 months ago.

Status:
NotEnoughInfo
Priority:
Normal
Assignee:
-
Category:
Usage
% Done:

0%


Description

In our verilog code, we have something similar to the below typedef:
typedef logic foo;

We then create both signal and structs using this typedef:

typedef struct {
  foo [7:0] field;
} bar;

If I look at bar.field in the vcd file generated, it is split into 8 separate bits.

However, if I just create the struct like below:

typedef struct {
  logic [7:0] field;
} bar;

I see what I expect in the vcd which is a unified 8 bit field.

Is there a way to recognize a typedef for the native bit, logic, reg, etc. and not cause this splitting?

History

#1 Updated by Wilson Snyder about 1 year ago

I don't see this behavior. Please add to test_regress/t/t_trace_complex.v to show the problem.

#2 Updated by Wilson Snyder 12 months ago

  • Status changed from New to AskedReporter

Still awaiting a test case... Thanks

#3 Updated by Wilson Snyder 6 months ago

  • Status changed from AskedReporter to NotEnoughInfo

Closing as no test case, feel free to post one and reopen.

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