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Issue #1276

vcd trace splits packed data type when it comes through a typedef

Added by Christopher Russell over 1 year ago. Updated about 1 month ago.

Status:
NotEnoughInfo
Priority:
Normal
Assignee:
-
Category:
Usage
% Done:

0%


Description

In our verilog code, we have something similar to the below typedef:
typedef logic foo;

We then create both signal and structs using this typedef:

typedef struct {
  foo [7:0] field;
} bar;

If I look at bar.field in the vcd file generated, it is split into 8 separate bits.

However, if I just create the struct like below:

typedef struct {
  logic [7:0] field;
} bar;

I see what I expect in the vcd which is a unified 8 bit field.

Is there a way to recognize a typedef for the native bit, logic, reg, etc. and not cause this splitting?

History

#1 Updated by Wilson Snyder over 1 year ago

I don't see this behavior. Please add to test_regress/t/t_trace_complex.v to show the problem.

#2 Updated by Wilson Snyder over 1 year ago

  • Status changed from New to AskedReporter

Still awaiting a test case... Thanks

#3 Updated by Wilson Snyder about 1 year ago

  • Status changed from AskedReporter to NotEnoughInfo

Closing as no test case, feel free to post one and reopen.

#4 Updated by Christopher Russell about 2 months ago

Sorry for the extremely delayed response. This is still affecting VCD output. I think I've distilled it to a much simpler test case. Structs are not actually necessary.

typedef logic foo;

module bar (
input foo [15:0] in,
output foo [15:0] out
);

assign out = in;

endmodule

If I look in the vcd, I will see this:
    $var wire  1 %+ out(0) $end
    $var wire  1 %, out(1) $end
    $var wire  1 %5 out(10) $end
    $var wire  1 %6 out(11) $end
    $var wire  1 %7 out(12) $end
    $var wire  1 %8 out(13) $end
    $var wire  1 %9 out(14) $end
    $var wire  1 %: out(15) $end
    $var wire  1 %- out(2) $end
    $var wire  1 %. out(3) $end
    $var wire  1 %/ out(4) $end
    $var wire  1 %0 out(5) $end
    $var wire  1 %1 out(6) $end
    $var wire  1 %2 out(7) $end
    $var wire  1 %3 out(8) $end
    $var wire  1 %4 out(9) $end

#5 Updated by Wilson Snyder about 2 months ago

I don't see this. Are you sure you're using the most recent version? If so, please submit a complete test case in test_regress format.

#6 Updated by Wilson Snyder about 2 months ago

Specifically I get:

$var wire 16 % in [15:0] $end
$var wire 16 & out [15:0] $end

#7 Updated by Christopher Russell about 1 month ago

I'll try to pull the latest version and see what happens. It's been a while since I updated verilator. I'll update once I confirm.

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