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Issue #1282

False UNOPTFLAT warning when using 2 interfaces with the same name on different hierarchies, connected to each-other with wire

Added by Yossi Nivin about 1 year ago. Updated about 1 year ago.

Status:
Assigned
Priority:
Normal
Assignee:
-
Category:
-
% Done:

0%


Description

I ran into false UNOPTFLAT warning while adding an interface to my design. After investigating it a little bit, I found out that the problem occurs when you are have another interface with the same type and name in a different hierarchy of the design, which is logically connected to the new interface.

I've build a simple test-case that shown the problem. To see the problem, extract the attached file and compile it:
verilator -Wall -cc tb.sv
I see the following warnings:
%Warning-UNOPTFLAT: b.sv:2: Signal unoptimizable: Feedback to clock or circular logic: tb.c_I.__Vcellout__b_i__sig
%Warning-UNOPTFLAT: Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
%Warning-UNOPTFLAT:      Example path: b.sv:2:  tb.c_I.__Vcellout__b_i__sig
%Warning-UNOPTFLAT:      Example path: c.sv:6:  ASSIGNW
%Warning-UNOPTFLAT:      Example path: test_if.sv:3:  tb.test_i.sig
%Warning-UNOPTFLAT:      Example path: b.sv:11:  ASSIGNW
%Warning-UNOPTFLAT:      Example path: b.sv:2:  tb.c_I.__Vcellout__b_i__sig
%Error: Exiting due to 1 warning(s)

If I change one of the interfaces name, the problems dissapere. Copy b_fixed.sv to b.sv and no warnings.

testcase.tgz - Testcase (488 Bytes) Yossi Nivin, 03/02/2018 04:29 PM

testcase.tgz (494 Bytes) Yossi Nivin, 03/02/2018 04:35 PM

testcase_updated.tgz - Updated testcase (494 Bytes) Yossi Nivin, 03/02/2018 04:38 PM

History

#1 Updated by Yossi Nivin about 1 year ago

#2 Updated by Yossi Nivin about 1 year ago

I accidentally uploaded the test-case after the fix. Please use the updated one.

#3 Updated by Wilson Snyder about 1 year ago

  • Status changed from New to Assigned

This hits a bug in the module inlining code. I'll take a look.

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