Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

scr1 test suite: built-in system functions only work when the return value is assigned #1285

Closed
veripoolbot opened this issue Mar 8, 2018 · 3 comments
Assignees
Labels
area: parser Issue involves SystemVerilog parsing resolution: fixed Closed; fixed

Comments

@veripoolbot
Copy link
Contributor


Author Name: Joel Holdsworth
Original Redmine Issue: 1285 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Building this test code fails...

module test();

string test;

initial begin
    // This works
    int ret = $value$plusargs("test_a=%s", test);  

    // This does not work
    $value$plusargs("test_b=%s", test);
end

endmodule

...with the following error...

%Error: test_task_returns_ignored.sv:11: syntax error, unexpected ';'          
%Error: Exiting due to 1 error(s)      
%Error: Command Failed /usr/local/bin/verilator_bin -sv --cc test_task_returns_ignored.sv   

@$value$plusargs()@, and other functions e.g. @$fscanf()@ fail in the same way when the return value is ignored.

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-03-09T04:42:11Z


Simple enough, mapped all system tasks to be allowed as functions. Thanks for the report.

Fixed in git towards 3.921.

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Joel Holdsworth
Original Date: 2018-03-09T17:20:58Z


Nice! Thanks for fixing it so quickly

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-03-17T16:03:33Z


In 3.922.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
area: parser Issue involves SystemVerilog parsing resolution: fixed Closed; fixed
Projects
None yet
Development

No branches or pull requests

2 participants