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Issue #1286

scr1 test suite: processing passes get stuck, and allocate huge amounts of system RAM when verilog contains memory blocks

Added by Joel Holdsworth about 1 year ago. Updated about 1 year ago.

Status:
Confirmed
Priority:
Normal
Assignee:
-
Category:
TranslationError
% Done:

0%


Description

Verilator gets stuck allocating huge amounts of memory when processing SystemVerilog code like this...

module test(input reset);

parameter MEM_POWER_SIZE = 16;
logic [7:0] memory [0:2**MEM_POWER_SIZE-1];

always @(negedge reset) begin
  memory = '{2**MEM_POWER_SIZE{'0}};
end

endmodule

History

#1 Updated by Wilson Snyder about 1 year ago

  • Status changed from New to Confirmed

Verilator needs enough memory to fit the entire model, times some inefficiency factor.

The fix could be to throw an error on very large structures (which of course should instead be sparse models), but it's hard to determine what is too large as that depends on system constraints. So my inclination is to leave it as is, but other ideas are welcome.

#2 Updated by Joel Holdsworth about 1 year ago

It would be nice to get an error or a warning. I only figured out the source of the problem by reading the file & line-number out of the AST in gdb.

I could try making the RAM block smaller. At the moment it's allocating more system RAM than I have; at least 2Gb. I'm not sure to what extent the test suite relies on this block being the size it is.

#3 Updated by Joel Holdsworth about 1 year ago

The block was 16Mb in size. Fortunately nothing in the test suite needs this much memory, so I reduced it to 64kB, and now Verilator is much happier

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