scr1 test suite: processing passes get stuck, and allocate huge amounts of system RAM when verilog contains memory blocks #1286
Labels
effort: days
Expect this issue to require roughly days of invested effort to resolve
Author Name: Joel Holdsworth
Original Redmine Issue: 1286 from https://www.veripool.org
Verilator gets stuck allocating huge amounts of memory when processing SystemVerilog code like this...
The text was updated successfully, but these errors were encountered: