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Issue #1287

scr1 test suite: SystemVerilog nested @ blocks are not supported

Added by Joel Holdsworth about 1 year ago. Updated about 1 year ago.

Status:
WillNotFix
Priority:
Normal
Assignee:
-
Category:
Unsupported
% Done:

0%


Description

The follow SystemVerilog code fails to parse...

module test(input clk);

initial begin
  @(posedge clk) begin
    $display("TEST");
  end
end

endmodule

...with the following error...

%Error: test_nested_at_block.sv:5: syntax error, unexpected '@'
%Error: Cannot continue
%Error: Command Failed /usr/local/bin/verilator_bin -sv --cc test_nested_at_block.sv

History

#1 Updated by Wilson Snyder about 1 year ago

  • Category set to Unsupported
  • Status changed from New to AskedReporter

Keeping open in case I'm misunderstanding what is needed...

Verilator is not an event based simulator and requires always blocks to be synthesizable, that is remove them from the initial block. This is unlikely to get fixed even in the medium term as is a fundamental rewrite.

#2 Updated by Joel Holdsworth about 1 year ago

Makes sense.

So here is the relevant code: https://github.com/syntacore/scr1/blob/master/src/tb/scr1_top_tb_ahb.sv#L104

Basically it reads test programs into the simulated memory, runs the CPU, until it halts, and logs the results.

Is there a way that this could be rewritten and maintain compatibility with the other simulators supported by this test-bench: ModelSim, Cadence, NCSim?

#3 Updated by Wilson Snyder about 1 year ago

  • Status changed from AskedReporter to WillNotFix

Turn it into a FSM, e.g.

int load_state;
initial begin
   load_state = 0;
   loader();
end
always @ (posedge_clk) loader();

task loader();
   if (load_state==0) begin
       stuff in existing initial block, e.g. open file
       if (need possedge loop) load_state = 1;
       else load_state = 2;  // May fallthru to below if
   end
   else if (load_state==1) begin
       stuff after posedge
       if end_of_posedge_loop load_state = 2;
   end
   // May have been set to 2 directly above 
   if (load_state==2) begin
       stuff to close file
   end

Of course many other ways to do something similar....

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