Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-03-09T04:50:44Z

Keeping open in case I'm misunderstanding what is needed...

Verilator is not an event based simulator and requires always blocks to be synthesizable, that is remove them from the initial block. This is unlikely to get fixed even in the medium term as is a fundamental rewrite.

Original Redmine Comment
Author Name: Joel Holdsworth
Original Date: 2018-03-09T17:06:04Z

Makes sense.

So here is the relevant code: https://github.com/syntacore/scr1/blob/master/src/tb/scr1_top_tb_ahb.sv#L104

Basically it reads test programs into the simulated memory, runs the CPU, until it halts, and logs the results.

Is there a way that this could be rewritten and maintain compatibility with the other simulators supported by this test-bench: ModelSim, Cadence, NCSim?

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-03-09T20:05:06Z

Turn it into a FSM, e.g.

int load_state;
initial begin
    load_state = 0;
    loader();
end
always @ (posedge_clk) loader();

task loader();
    if (load_state==0) begin
        stuff in existing initial block, e.g. open file
        if (need possedge loop) load_state = 1;
        else load_state = 2;  // May fallthru to below if
    end
    else if (load_state==1) begin
        stuff after posedge
        if end_of_posedge_loop load_state = 2;
    end
    // May have been set to 2 directly above 
    if (load_state==2) begin
        stuff to close file
    end

Of course many other ways to do something similar....