scr1 test suite: SystemVerilog nested @ blocks are not supported #1287
Labels
resolution: wontfix
Closed; work won't continue on an issue or pull request
type: feature-IEEE
Request to add new feature, described in IEEE 1800
Author Name: Joel Holdsworth
Original Redmine Issue: 1287 from https://www.veripool.org
The follow SystemVerilog code fails to parse...
...with the following error...
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