scr1 test suite: assert properties don't work
module test(); mycheck : assert property ( 1'b1 ) else begin $error("WTF"); end endmodule...with the following error...
%Error: test_assert_property.sv:4: syntax error, unexpected assert, expecting cover %Error: Cannot continue %Error: Command Failed /usr/local/bin/verilator_bin -sv --lint-only test_assert_property.sv
#1 Updated by John Coiner 10 months ago
I'm working on issue 785 which could be considered a dup:
Though that issue is old, I'm actively working it this week.
Do you really need support for non-edge-triggered asserts? Right now I already have support for edge-triggered asserts of this form:
assert property ((@ posedge clk) expr) [ else statements... ];
... with 'edge' and 'negedge' also supported. I don't have purely combinational asserts working yet, that's more work.
#2 Updated by John Coiner 10 months ago
For that matter, does verilog even permit unclocked 'assert property' statements? I'm no language lawyer, and I don't have access to a IEEE spec or a copy of "the binary spec" aka VCS or NC.
Online slide decks I've found only show examples of clocked assertions, though.
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