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Issue #1290

scr1 test suite: assert properties don't work

Added by Joel Holdsworth about 1 year ago. Updated about 1 year ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
Lint
% Done:

0%


Description

The following SystemVerilog code fails to build...
module test();

mycheck : assert property (
  1'b1
) else begin
  $error("WTF");
end

endmodule
...with the following error...
%Error: test_assert_property.sv:4: syntax error, unexpected assert, expecting cover
%Error: Cannot continue
%Error: Command Failed /usr/local/bin/verilator_bin -sv --lint-only test_assert_property.sv

Related issues

Duplicates Issue #785: Support for SystemVerilog assertions Closed

History

#1 Updated by John Coiner about 1 year ago

Hi Joel,

I'm working on issue 785 which could be considered a dup:

https://www.veripool.org/issues/785-Verilator-Support-for-SystemVerilog-assertions

Though that issue is old, I'm actively working it this week.

Do you really need support for non-edge-triggered asserts? Right now I already have support for edge-triggered asserts of this form:

assert property ((@ posedge clk) expr) [ else statements... ];

... with 'edge' and 'negedge' also supported. I don't have purely combinational asserts working yet, that's more work.

Thanks,

John

#2 Updated by John Coiner about 1 year ago

For that matter, does verilog even permit unclocked 'assert property' statements? I'm no language lawyer, and I don't have access to a IEEE spec or a copy of "the binary spec" aka VCS or NC.

Online slide decks I've found only show examples of clocked assertions, though.

#3 Updated by Joel Holdsworth about 1 year ago

You're right - the scr1 tests are all clocked. My example was a bit too simplified!

Great news that you're working on this this week. I'll be glad to test your patches with scr1.

#4 Updated by John Coiner about 1 year ago

Thanks. I discovered that concurrent asserts are always clocked in verilog.

So this is a dup of 785.

#5 Updated by John Coiner about 1 year ago

  • Duplicates Issue #785: Support for SystemVerilog assertions added

#6 Updated by Wilson Snyder about 1 year ago

  • Status changed from New to Confirmed
  • Assignee set to John Coiner

John, thanks for looking.

#7 Updated by John Coiner about 1 year ago

Here's the fix.

commit c8cf2afb15860722e19c4ea6dd7ca0bc74010fac (HEAD -> master, origin/master, origin/HEAD) Author: Wilson Snyder <> Date: Sun Mar 11 10:37:20 2018 -0400

Support assert properties, bug785, bug1290.

#8 Updated by John Coiner about 1 year ago

  • Status changed from Confirmed to Closed

#9 Updated by John Coiner about 1 year ago

Fixed in git towards 3.922

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