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scr1 test suite: assert properties don't work #1290
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Original Redmine Comment Hi Joel, I'm working on issue 785 which could be considered a dup: https://www.veripool.org/issues/785-Verilator-Support-for-SystemVerilog-assertions Though that issue is old, I'm actively working it this week. Do you really need support for non-edge-triggered asserts? Right now I already have support for edge-triggered asserts of this form: assert property ((@ posedge clk) expr) [ else statements... ]; ... with 'edge' and 'negedge' also supported. I don't have purely combinational asserts working yet, that's more work. Thanks, John |
Original Redmine Comment For that matter, does verilog even permit unclocked 'assert property' statements? I'm no language lawyer, and I don't have access to a IEEE spec or a copy of "the binary spec" aka VCS or NC. Online slide decks I've found only show examples of clocked assertions, though. |
Original Redmine Comment You're right - the scr1 tests are all clocked. My example was a bit too simplified! Great news that you're working on this this week. I'll be glad to test your patches with scr1. |
Original Redmine Comment Thanks. I discovered that concurrent asserts are always clocked in verilog. So this is a dup of 785. |
Original Redmine Comment John, thanks for looking. |
Original Redmine Comment Here's the fix. commit c8cf2af (HEAD -> master, origin/master, origin/HEAD)
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Original Redmine Comment Fixed in git towards 3.922 |
Author Name: Joel Holdsworth
Original Redmine Issue: 1290 from https://www.veripool.org
Original Assignee: John Coiner (@jcoiner)
The following SystemVerilog code fails to build...
...with the following error...
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