Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Issue #1291

scr1 test suite: delayed always blocks are unsupported

Added by Joel Holdsworth about 1 year ago. Updated about 1 year ago.

Status:
WillNotFix
Priority:
Normal
Assignee:
-
Category:
Unsupported
% Done:

0%


Description

This code generates a warning:
module test();               

reg clk = 0;                 
always #123 clk = !clk;      

endmodule
%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.            
%Error: Exiting due to 1 warning(s)                        
%Error: See the manual and http://www.veripool.org/verilator for more assistance.                                      
%Error: Command Failed /usr/local/bin/verilator_bin -sv --lint-only test_always_delay.sv

Would it be possible to support delayed always blocks that lack sensitivity lists?

History

#1 Updated by Joel Holdsworth about 1 year ago

RTFM.... I see this isn't going to work

#2 Updated by Wilson Snyder about 1 year ago

  • Status changed from New to WillNotFix

Correct, clocks must come from the C side. At least until events are supported which is long off.

Note you can turn off the warning but that won't help the intent of this case.

Also available in: Atom