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scr1 test suite: delayed always blocks are unsupported #1291

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veripoolbot opened this issue Mar 10, 2018 · 2 comments
Closed

scr1 test suite: delayed always blocks are unsupported #1291

veripoolbot opened this issue Mar 10, 2018 · 2 comments
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resolution: wontfix Closed; work won't continue on an issue or pull request type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Joel Holdsworth
Original Redmine Issue: 1291 from https://www.veripool.org


This code generates a warning:

module test();               

reg clk = 0;                 
always #123 clk = !clk;      

endmodule

%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.            
%Error: Exiting due to 1 warning(s)                        
%Error: See the manual and http://www.veripool.org/verilator for more assistance.                                      
%Error: Command Failed /usr/local/bin/verilator_bin -sv --lint-only test_always_delay.sv

Would it be possible to support delayed always blocks that lack sensitivity lists?

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Original Redmine Comment
Author Name: Joel Holdsworth
Original Date: 2018-03-10T16:16:58Z


RTFM.... I see this isn't going to work

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-03-10T17:50:40Z


Correct, clocks must come from the C side. At least until events are supported which is long off.

Note you can turn off the warning but that won't help the intent of this case.

@veripoolbot veripoolbot added resolution: wontfix Closed; work won't continue on an issue or pull request type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
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Labels
resolution: wontfix Closed; work won't continue on an issue or pull request type: feature-IEEE Request to add new feature, described in IEEE 1800
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